Abstract: A cold cathode field emission display is described. A key feature of its design is that each individual microtip has its own ballast resistor. The latter is formed from a resistive layer that has been interposed between the cathode line and the substrate. When openings for the microtips are formed in the gate line, extending down as far as the resistive layer, an overetching step is introduced. This causes the dielectric layer to be substantially undercut immediately above the resistive layer thereby creating an annular resistor positioned between the gate line and the base of the microtip.

Abstract: A method for fabricating high aspect ratio spacers for a field emission display is described. An array of field emission microtips is formed over a substrate. A layer of lithographic material is formed over the array of field emission microtips. Openings are formed in the layer of lithographic material. The openings may be formed by a plasma etch with oxygen, or by x-ray lithography. A non-outgassing material is formed over the surface of the layer of lithographic material, including in the openings. The openings are filled with a spacer material, the spacer material being a conductive material, an insulator, or, preferably, a combination thereof. Lastly, the layer of lithographic material and the non-outgassing material are removed.

Abstract: A microtip structure with high uniformity, low operating voltage and no resistive dissipation for a field emission display is described. A substrate is provided. A first conductive layer is formed on the substrate that acts as a cathode. A second conductive layer with a narrow circular opening acts as a gate. A first dielectric layer separates the cathode and the gate. The microtip extends up from the cathode and into the opening. A second dielectric layer is over the gate, with a circular opening that is larger than and concentric with the narrow circular opening in the gate. A means to provide a brief, charging voltage to the gate, followed by a longer operational voltage, wherein the amplitude of the operational voltage is lower than the amplitude of the charging voltage, is included.

Abstract: A high resolution matrix addressed flat panel display having single field emission microtip redundancy with resistive base is described. Parallel, spaced conductors acting as cathode columns for the display are over the substrate. A layer of insulation is formed over the cathode columns. Parallel, spaced conductors acting as gate lines for the display are formed over the layer of insulation at a right angle to the cathode columns. The intersections of the cathode columns and gate lines are pixels of the display. A plurality of openings at the pixels extend through the insulating layer and the gate lines. At each of the openings is a resistive base connected to the cathode conductor column. A small field emission microtip is formed on each resistive base, extending up from the resistive base and into the openings, the height of the microtip being many times smaller than the height of the resistive base.

Abstract: A method for making a matrix addressed flat panel display using field emission microtips having reduced capacitance and low power consumption, and the resulting display, are described. A dielectric base substrate on which to form the field emission microtips is provided. Cathode columns of parallel spaced conductors are formed upon the substrate. First dielectric supports are formed in and above spaces between the cathode columns. Gate lines for the display are formed of parallel spaced conductors over the supports and perpendicular to the supports and the cathode columns. Second dielectric supports are formed below spaces between the gate lines, on the cathode columns and intersecting with the first supports. Pixels of the display are formed at the intersections of the cathode columns and the gate lines. There are a plurality of openings in the gate lines, at the pixels.

Abstract: A surface electron barrier region is formed on a semiconductor membrane device by a single step laser process which produces a sharp doping profile in a surface region above the light penetration depth. Enhanced quantum efficiency is observed, and by selectively forming barrier layers of differing depth, a CCD device architecture for two-color sensitivity is achieved. The barrier layer results in enhanced membrane-type and radiation hardened bipolar and CMOS devices.