Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices.

Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices.

Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices.