Patents by Inventor Jan A. Wikstrom

Jan A. Wikstrom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7071736
    Abstract: A method and apparatus of precharging data and/or address lines each having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the precharge circuit based on a previous logical value on the line being precharged. In some embodiments, a driver circuit drives an output node either high or low during a first phase of each clock cycle, and a precharge circuit then precharges the output node to an intermediate voltage during a second phase of the clock cycle in preparation for the following clock cycle. Some embodiments include source-follower configured FETs to precharge, wherein these FETs turn off once the output voltage reaches an intermediate value.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: July 4, 2006
    Assignee: Cray Inc.
    Inventor: Jan A. Wikstrom
  • Publication number: 20040233752
    Abstract: A method and apparatus of precharging data and/or address lines each having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the precharge circuit based on a previous logical value on the line being precharged. In some embodiments, a driver circuit drives an output node either high or low during a first phase of each clock cycle, and a precharge circuit then precharges the output node to an intermediate voltage during a second phase of the clock cycle in preparation for the following clock cycle. Some embodiments include source-follower configured FETs to precharge, wherein these FETs turn off once the output voltage reaches an intermediate value.
    Type: Application
    Filed: May 17, 2004
    Publication date: November 25, 2004
    Applicant: Cray Inc.
    Inventor: Jan A. Wikstrom
  • Patent number: 5182473
    Abstract: Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.
    Type: Grant
    Filed: January 22, 1992
    Date of Patent: January 26, 1993
    Assignee: Cray Research, Inc.
    Inventors: Jan A. Wikstrom, Mark S. Birrittella, David Kiefer, Stephen B. Smetana, Vernon W. Swanson
  • Patent number: 4964081
    Abstract: A READ-WHILE-WRITE current-mode logic RAM cell suitable for use in a RAM device having the ability to simultaneously write and read data.The RAM cell contains a bit-cell consisting of flip-flop configured transistors differentially connected to a constant current source, a multiple-emitter transistor network tied to each bit-cell load resistor which prevents the bit-cell from saturating, separate READ and WRITE data lines, and READ and WRITE buffer transistors having READ and WRITE control lines.
    Type: Grant
    Filed: August 11, 1989
    Date of Patent: October 16, 1990
    Assignee: Cray Research, Inc.
    Inventors: Mark S. Birrittella, Jan A. Wikstrom