Patents by Inventor Jan-Bernd Themann

Jan-Bernd Themann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multicore communication processing
    Patent number: 7715428
    Abstract: Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Herman D. Dierks, Jr., Christoph Raisch, Jan-Bernd Themann, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
  • System and Method for Multicore Communication Processing
    Publication number: 20080181245
    Abstract: A system and method for multicore processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Inventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Herman D. Dierks, Christoph Raisch, Jan-Bernd Themann, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli