Abstract: A vertically stacked image sensor with HDR imaging functionality and a method of operating the same are disclosed. The image sensor comprises, a first substrate, a pixel array organized into a plurality of pixel subarrays, of which each pixel comprises a photoelectric element for integrating a photocharge during each one of a plurality of subframe exposures, a transfer gate and a buffered charge-voltage converter. A first charge accumulation element of the charge-voltage converter is operatively connectable to at least one second charge accumulation element through a gain switch. The image sensor comprises control circuitry configured to trigger a partial or a complete transfer of the and to time-interleave at least two rolling shutter control sequences. Separate readout blocks are provided on the second substrate for each pixel subarray, each comprising in a pipelined architecture an A/D conversion unit, a pixel memory logic and a pixel memory unit.

Abstract: A pixel for a global shutter pixel array includes a sensing layer and a storage layer. The sensing layer has a sensing element adapted to provide charges upon receiving radiation and a floating diffusion region for receiving charges from the sensing element. The storage layer has at least one storage node for receiving charges from the sensing layer's floating diffusion region and storing the charges. The sensing layer and storage layer form a stack of layers, the sensing layer covering at least the storage node of the storage layer, and the stack has a light shield between the sensing layer and the storage node of the storage layer, so the storage node is shielded from impinging radiation. The storage node is between two transfer gates. The storage node and its surrounding gates are provided between the first floating diffusion region and a second floating diffusion region.

Abstract: To provide a TOF sensor equipped with a wiring structure that makes it possible to reduce pixel-by-pixel variation in the propagation delay time of a high-speed clock signal connected to the transfer gate of each pixel. This TOF sensor 200 comprises a pixel area 30 and a clock buffer area 20 arranged on one end side of the pixel area in the Y-direction thereof. Single pixels 40 or unit pixel groups 36 configured from a plurality of pixels are arranged in a two-dimensional matrix in the pixel area 30, a plurality of clocks for driving transfer gates 42 are each binarily split in the X-direction in the clock buffer area 20 and input to a final stage clock buffer 22 for driving unit pixel group rows 35 in which the unit pixel groups 36 are arranged in the Y-direction, and the output of the clock buffer 22 is binarily split in the Y-direction and connected to the transfer gates 42 of the unit pixel group rows 35.

Abstract: A vertically stacked image sensor with HDR imaging functionality and a method of operating the same are disclosed. The image sensor comprises, a first substrate, a pixel array organized into a plurality of pixel subarrays, of which each pixel comprises a photoelectric element for integrating a photocharge during each one of a plurality of subframe exposures, a transfer gate and a buffered charge-voltage converter. A first charge accumulation element of the charge-voltage converter is operatively connectable to at least one second charge accumulation element through a gain switch. The image sensor comprises control circuitry configured to trigger a partial or a complete transfer of the and to time-interleave at least two rolling shutter control sequences. Separate readout blocks are provided on the second substrate for each pixel subarray, each comprising in a pipelined architecture an A/D conversion unit, a pixel memory logic and a pixel memory unit.

Abstract: A pixel for a global shutter pixel array includes a sensing layer and a storage layer. The sensing layer has a sensing element adapted to provide charges upon receiving radiation and a floating diffusion region for receiving charges from the sensing element. The storage layer has at least one storage node for receiving charges from the sensing layer's floating diffusion region and storing the charges. The sensing layer and storage layer form a stack of layers, the sensing layer covering at least the storage node of the storage layer, and the stack has a light shield between the sensing layer and the storage node of the storage layer, so the storage node is shielded from impinging radiation. The storage node is between two transfer gates. The storage node and its surrounding gates are provided between the first floating diffusion region and a second floating diffusion region.

Abstract: A shared-pixel circuit includes first and second pixel cells. The pixel cells comprise a photosensitive element, a charge storage area operatively connectable to the photosensitive element, an amplification transistor, and a select switch coupled between the amplification transistor and a column bus. The amplification transistors of the first and second pixel cells are arranged to form an input pair of a differential amplifier configured for receiving one of a first and second sensing signal, representative of the charge stored in the charge storage area of the first and second pixel cells respectively, and an analog signal having a ramped signal portion, as a first input signal, receiving the other one of the first and second sensing signal and the analog signal as a second input signal, comparing the first input signal to the second input signal, and generating a bi-stable output signal based on the comparing of the input signals.

Abstract: An image sensor is proposed to have a stack with at least a pixel array tier and a control logic tier. The pixel array tier comprises an array of pixels which are arranged into pixel columns n, each pixel column n comprising a number of N sub-columns: Each sub-column is denoted by N(n,i) with 1?i?N. The control logic tier comprises an array of analog-to-digital-converters which are arranged into ADC columns m, wherein each analog-to-digital converter comprises a number of M stages. Each stage is denoted by M(m,j) with 1?j?M, Furthermore, each respective sub-column N(n,i) is electrically connected to a dedicated stage M(m,j=i) and the stages M(m,j) are electrically interconnected to form the analog-to-digital converters, respectively. The control logic tier is arranged to sequentially read out the sub-columns N(n,i), wherein the stages M(m,j=i) dedicated to the sub-columns N(n,i) are arranged as input stages to sequentially receive signal levels of the pixels in the sub-columns N(n,i), respectively.

Abstract: An image sensor is proposed to have a stack with at least a pixel array tier and a control logic tier. The pixel array tier comprises an array of pixels which are arranged into pixel columns n, each pixel column n comprising a number of N sub-columns: Each sub-column is denoted by N(n,i) with 1?i?N. The control logic tier comprises an array of analog-to-digital-converters which are arranged into ADC columns m, wherein each analog-to-digital converter comprises a number of M stages. Each stage is denoted by M(m,j) with 1?j?M, Furthermore, each respective sub-column N(n,i) is electrically connected to a dedicated stage M(m,j=i) and the stages M(m,j) are electrically interconnected to form the analog-to-digital converters, respectively. The control logic tier is arranged to sequentially read out the sub-columns N(n,i), wherein the stages M(m,j=i) dedicated to the sub-columns N(n,i) are arranged as input stages to sequentially receive signal levels of the pixels in the sub-columns N(n,i), respectively.

Abstract: An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M3 connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M4 connected between the first sense node A and the second sense node B; and a buffer amplifier M1 having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS1 and a second reset control line RS2 to continuously switch on one of the first reset transistor M3 and the second reset transistor M4 during a readout period of an operational cycle of the pixels.

Abstract: An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M3 connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M4 connected between the first sense node A and the second sense node B; and a buffer amplifier M1 having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS1 and a second reset control line RS2 to continuously switch on one of the first reset transistor M3 and the second reset transistor M4 during a readout period of an operational cycle of the pixels.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: A pixel comprises a pinned photodiode for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the pinned photodiode and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Abstract: A pixel structure comprises a photo-sensitive element PPD for generating charges in response to light and a charge conversion element FD. A first transfer gate TX is connected between the photo-sensitive element PPD and the charge conversion element. A charge storage element PG is connected to the photo-sensitive element PPD. The charge storage element PG has a higher charge storage density than the photo-sensitive element PPD. The charge storage element PG is located on the photo-sensitive element PPD side of the first transfer gate TX and is arranged to collect charges generated by the photo-sensitive element PPD during an integration period. The charge storage element can be a photo gate, photodiode or capacitor. Arrangements are provided with, and without, a potential barrier between the photo-sensitive element PPD and the charge storage element PG.

Abstract: A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.