Abstract: A transistor circuit comprising a first differential amplifier which is composed of a differential pair and a current mirror. The transistor circuit further comprises a second differential amplifier which measures a differential offset voltage in the first differential amplifier and reduces this offset voltage by means of common mode current feedback. The transistor circuit thus provides a stable amplifier having a high speed and a low offset voltage which can be used advantageously in a logic output buffer so that, for example, an ECL output buffer can be realized in CMOS.

Abstract: An integrated circuit comprising logic circuits and at least one push-pull stage. In order to reduce the magnitude of induction voltages on power supply lines of the circuit, caused by the current variations in the push-pull stage comprising a push transistor and a pull transistor, a first current through one transistor is kept substantially constant until after a most significant rise of a second current through the other transistor when the push-pull stage is switched. A push-pull stage produces lower induction voltages during switching can thus be realized without adversely affecting the switching speed.

Abstract: The invention relates to an additional transistor which is connected in cascode with a sub-circuit of a logic circuit in order to protect further transistors of the sub-circuit against hot carrier stress and hot carrier degradation. In a logic circuit having transistors of a first conductivity type, an additional transistor of the second conductivity type is arranged in cascode. This additional transistor is connected as a diode or as a current source in dependence on an output voltage of the circuit. Further aspects of the invention concern the switching means for switching the additional transistor and the location where the additional transistor is to be inserted.

Abstract: In integrated logic circuits, at least one additional transistor may be provided in cascode connection with at least one other component in order to avoid detrimentally high electrical fields in components of such circuits. The control electrode is then connected to one of the power supply lines. When the state of the logic circuit changes, switching currents generate voltage peaks on the power supply lines due to the inductance of these lines. Via the chip capacitance these voltage peaks jump from one power supply line to the other. Thus, a positive feedback loop is formed which comprises one power supply line, the chip capacitance, the other power supply line and the additional transistor. Instabilities in such circuits are damped by inserting a resistance element between the control electrode of the additional transistor and the power supply line coupled thereto.

Abstract: A digital circuit with a 5 V power supply voltage in which NMOS transistors constructed in sub-micron technology are protected against excessive field strengths by means of additional transistors in order to prevent so-called "hot carrier stress" for this purpose the additional transistors have a greater channel length and/or a higher threshold voltage.