Patents by Inventor Jan Grabinski
Jan Grabinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11275879Abstract: A simulation method and a corresponding medium storing processor-executable code for detecting a high impedance net within an electronic circuit comprising a plurality of transistors is presented. The simulation method includes the step of connecting programmable resistors between two terminals of each transistor. Subsequently, voltage fluctuations are determined at the first terminals of a first group of transistors, where the voltage fluctuations are caused by connecting the programmable resistors. By connecting current sources with the first terminals of the first group of transistors, a potentially hazardous high impedance net may be detected within the electronic circuit.Type: GrantFiled: July 13, 2017Date of Patent: March 15, 2022Assignee: Diatog Semiconductor (UK) LimitedInventor: Jan Grabinski
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Patent number: 11239836Abstract: A circuit and a method for providing a switchable current linkage between a first terminal and a second terminal is presented. The circuit has a transistor switch and a charge pump circuit. An output node of the charge pump circuit is coupled to a control terminal of the transistor device, and an input node of the charge pump circuit is coupled to a predetermined voltage. The charge pump generates a boosted voltage. A drive circuit provides feedback control for the current flowing through the transistor. The drive circuit also controls the voltage magnitude at the input node of the charge pump circuit in accordance with the feedback control or to control a magnitude of a voltage at the control terminal of the transistor device in accordance with the feedback control.Type: GrantFiled: April 21, 2020Date of Patent: February 1, 2022Assignee: Dialog Semiconductor (UK) LimitedInventors: Jerome Sanchez, Fabio Rigoni, Jan Grabinski, Ali Zahabi
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Patent number: 10969810Abstract: A voltage regulator and a method are presented. The regulator has a pass device coupled to an input node at an input voltage. Furthermore, the voltage regulator has a regulator circuit to control the pass device to provide a regulated output voltage at an output node based on the input voltage. Components of the regulator circuit are arranged and operated between the input node and the output node. The voltage regulator allows a load of the voltage regulator to be arranged between the output node and a reference node at a reference voltage, wherein the reference voltage differs from the output voltage.Type: GrantFiled: April 2, 2019Date of Patent: April 6, 2021Assignee: Dialog Semiconductor (UK) LimitedInventors: Jan Grabinski, Frank Kronmueller
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Patent number: 10666245Abstract: A circuit and a method for providing a switchable current linkage between a first terminal and a second terminal is presented. The circuit has a transistor switch and a charge pump circuit An output node of the charge pump circuit is coupled to a control terminal of the transistor device, and an input node of the charge pump circuit is coupled to a predetermined voltage. The charge pump generates a boosted voltage. A drive circuit provides feedback control for the current flowing through the transistor. The drive circuit also controls the voltage magnitude at the input node of the charge pump circuit in accordance with the feedback control or to control a magnitude of a voltage at the control terminal of the transistor device in accordance with the feedback control.Type: GrantFiled: July 19, 2018Date of Patent: May 26, 2020Assignee: Dialog Semiconductor (UK) LimitedInventors: Jerome Sanchez, Fabio Rigoni, Jan Grabinski, Ali Zahabi
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Publication number: 20200117225Abstract: A voltage regulator and a method are presented. The regulator has a pass device coupled to an input node at an input voltage. Furthermore, the voltage regulator has a regulator circuit to control the pass device to provide a regulated output voltage at an output node based on the input voltage. Components of the regulator circuit are arranged and operated between the input node and the output node. The voltage regulator allows a load of the voltage regulator to be arranged between the output node and a reference node at a reference voltage, wherein the reference voltage differs from the output voltage.Type: ApplicationFiled: April 2, 2019Publication date: April 16, 2020Inventors: Jan Grabinski, Frank Kronmueller
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Publication number: 20190028095Abstract: A circuit and a method for providing a switchable current linkage between a first terminal and a second terminal is presented. The circuit has a transistor switch and a charge pump circuit An output node of the charge pump circuit is coupled to a control terminal of the transistor device, and an input node of the charge pump circuit is coupled to a predetermined voltage. The charge pump generates a boosted voltage. A drive circuit provides feedback control for the current flowing through the transistor. The drive circuit also controls the voltage magnitude at the input node of the charge pump circuit in accordance with the feedback control or to control a magnitude of a voltage at the control terminal of the transistor device in accordance with the feedback control.Type: ApplicationFiled: July 19, 2018Publication date: January 24, 2019Inventors: Jerome Sanchez, Fabio Rigoni, Jan Grabinski, Ali Zahabi
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Publication number: 20190018059Abstract: A simulation method and a corresponding medium storing processor-executable code for detecting a high impedance net within an electronic circuit comprising a plurality of transistors is presented. The simulation method includes the step of connecting programmable resistors between two terminals of each transistor. Subsequently, voltage fluctuations are determined at the first terminals of a first group of transistors, where the voltage fluctuations are caused by connecting the programmable resistors. By connecting current sources with the first terminals of the first group of transistors, a potentially hazardous high impedance net may be detected within the electronic circuit.Type: ApplicationFiled: July 13, 2017Publication date: January 17, 2019Inventor: Jan Grabinski
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Patent number: 9571080Abstract: Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit is configured to generate an error signal depending on a comparison of the reference clock signal and a feedback signal. Furthermore, the delay-locked loop circuit generates the feedback signal depending on the error signal and on the main clock signal.Type: GrantFiled: August 4, 2015Date of Patent: February 14, 2017Assignee: Synopsys, Inc.Inventor: Jan Grabinski
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Publication number: 20160036426Abstract: Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit is configured to generate an error signal depending on a comparison of the reference clock signal and a feedback signal. Furthermore, the delay-locked loop circuit generates the feedback signal depending on the error signal and on the main clock signal.Type: ApplicationFiled: August 4, 2015Publication date: February 4, 2016Inventor: Jan Grabinski
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Patent number: 8884671Abstract: A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.Type: GrantFiled: April 11, 2014Date of Patent: November 11, 2014Assignee: Synopsys, Inc.Inventor: Jan Grabinski
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Publication number: 20140306741Abstract: A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.Type: ApplicationFiled: April 11, 2014Publication date: October 16, 2014Applicant: Synopsys, Inc.Inventor: Jan Grabinski