Abstract: A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store.

Abstract: A digital data processing system that is designed to facilitate use of UML activity diagrams.

Abstract: A digital data processing system that is designed to facilitate use of UML activity diagrams.

Abstract: An interface requests instructions from a data store storing instructions of an application to be processed by a data processor, and receives and transmits the instructions to the data processor. The interface includes: an input that receives the instructions from the data store via at least one input bus; a buffer that stores received instructions; an output that outputs instructions to the data processing apparatus via the output bus; a control signal input that receives a control signal; and a buffer controller that controls the buffer to request an instruction subsequent to a previously received instruction within an instruction stream of the application from the data store in response to detection of no control signal on the control signal input and to detection of available buffer storage capacity.

Abstract: A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store.

Abstract: A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.

Abstract: An interface operable to request instructions from a data store storing instructions of an application to be processed by a data processor, and operable to receive and transmit said instructions to said data processor, said interface comprising: an input operable to receive said instructions from said data store via at least one input bus; a buffer operable to store said received instructions; an output operable to output said instructions to said data processing apparatus via at least one output bus; a control signal input operable to receive a control signal; and a buffer controller operable to: control said buffer to request an instruction subsequent to a previously received instruction within an instruction stream of said application from said data store in response to detection of no control signal on said control signal input and to detection of available buffer storage capacity; and in response to a control signal received at said control signal input, said controller is operable to control at least on

Abstract: A processor is described including a plurality of data path elements 2, 4, 6, 8 which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.

Abstract: A method and apparatus for optimizing the compilation of a computer program by exposing parallelism are disclosed. Information describing the operations in the program and their sequence is extracted and stored in a data structure. The operations in the program which involve index expressions are identified and symbolically executed, producing information describing the memory accesses by the program. Operations which can be executed in parallel are identified based on the information describing memory accesses. The program is interrogated with questions in a question data structure relating to how the program accesses memory. The answers to the questions are accumulated in index sets and back annotated into the question data structure.

Abstract: A method and apparatus for optimizing the compilation of computer program by exposing parallelism are disclosed. The computer program contains steps which involve index expressions. The program also involves function calls. An index path in the program is identified by noting the steps involving index expressions. A non-hierarchical representation of the index path, including operations in the function calls is created and interrogated with questions relating to memory accesses. The results of the interrogation are stored in or back annotated to a question data structure. The method and apparatus preferably involve the use of a signal flow graph which is completed using the information in the question data structure.