Patents by Inventor Jan Gulpen
Jan Gulpen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10431476Abstract: A method of making a plurality of packaged semiconductor devices. The method includes providing a carrier blank having a die receiving surface and an underside. The method also includes mounting a plurality of semiconductor dies on the die receiving surface, wherein the dies extend to a first height above the die receiving surface. The method further includes depositing an encapsulant on the die receiving surface, wherein an upper surface of the encapsulant is located above said first height. The method also includes singulating to form the plurality of packaged semiconductor devices by sawing into the underside, through the carrier blank and partially through the encapsulant to a depth intermediate the first height and the upper surface, wherein said sawing separates the carrier blank into a plurality of carriers, and removing encapsulant from the upper surface of the encapsulant at least until said saw depth is reached.Type: GrantFiled: March 26, 2018Date of Patent: October 1, 2019Assignee: NXP B.V.Inventors: Jetse de Witte, Antonius Hendrikus Jozef Kamphuis, Jan Gulpen
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Patent number: 10109564Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.Type: GrantFiled: February 13, 2017Date of Patent: October 23, 2018Assignee: NXP B.V.Inventors: Roelf Groenhuis, Leo Van Gemert, Tonny Kamphuis, Jan Gulpen
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Publication number: 20180301353Abstract: A method of making a plurality of packaged semiconductor devices. The method includes providing a carrier blank having a die receiving surface and an underside. The method also includes mounting a plurality of semiconductor dies on the die receiving surface, wherein the dies extend to a first height above the die receiving surface. The method further includes depositing an encapsulant on the die receiving surface, wherein an upper surface of the encapsulant is located above said first height. The method also includes singulating to form the plurality of packaged semiconductor devices by sawing into the underside, through the carrier blank and partially through the encapsulant to a depth intermediate the first height and the upper surface, wherein said sawing separates the carrier blank into a plurality of carriers, and removing encapsulant from the upper surface of the encapsulant at least until said saw depth is reached.Type: ApplicationFiled: March 26, 2018Publication date: October 18, 2018Inventors: Jetse de Witte, Antonius Hendrikus Jozef Kamphuis, Jan Gulpen
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Patent number: 10096555Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.Type: GrantFiled: March 20, 2017Date of Patent: October 9, 2018Assignee: NXP B.V.Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
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Publication number: 20170372988Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.Type: ApplicationFiled: February 13, 2017Publication date: December 28, 2017Inventors: ROELF GROENHUIS, LEO VAN GEMERT, TONNY KAMPHUIS, JAN GULPEN
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Publication number: 20170213797Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.Type: ApplicationFiled: March 20, 2017Publication date: July 27, 2017Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
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Patent number: 9653414Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.Type: GrantFiled: July 22, 2015Date of Patent: May 16, 2017Assignee: NXP B. V.Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
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Publication number: 20170103939Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device. The method comprises providing a lead frame, the lead frame having I/O terminals surrounding a die attach region, the lead frame defined onto a temporary carrier. A device die is attached onto the die-attach region. The device die is wire bonded to the I/O terminals, the I/O terminals located in a first position. In a molding compound the wire-bonded device die and lead frame are encapsulated. The temporary carrier is removed from the lead frame, underside surfaces of the device die and I/O terminals are exposed. Applying a non-conductive layer to the exposed underside surfaces of the device die and I/O terminals, thereby defines features in which conductive traces may be defined from the I/O terminals in the first position to customized I/O terminals located in a second position.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis
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Publication number: 20170025369Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.Type: ApplicationFiled: July 22, 2015Publication date: January 26, 2017Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
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Patent number: 9379071Abstract: Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.Type: GrantFiled: April 17, 2014Date of Patent: June 28, 2016Assignee: NXP B.V.Inventors: Tonny Kamphuis, Jan Gulpen, Jan Willem Bergman
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Publication number: 20150303156Abstract: Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.Type: ApplicationFiled: April 17, 2014Publication date: October 22, 2015Applicant: NXP B.V.Inventors: Tonny Kamphuis, Jan Gulpen, Jan Willem Bergman
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Patent number: 8679963Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.Type: GrantFiled: June 12, 2013Date of Patent: March 25, 2014Assignee: NXP B.V.Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo Van Gemert, Eric Van Grunsven, Marc De Samber
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Publication number: 20130273731Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.Type: ApplicationFiled: June 12, 2013Publication date: October 17, 2013Inventors: Jan GULPEN, Tonny KAMPHUIS, Pieter HOCHSTENBACH, Leo VAN GEMERT, Eric Van GRUNSVEN, Marc De SAMBER
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Patent number: 8482136Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.Type: GrantFiled: December 29, 2009Date of Patent: July 9, 2013Assignee: NXP B.V.Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber
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Publication number: 20110156237Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: NXP B.V.Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber