Patents by Inventor Jan H. Achrenius

Jan H. Achrenius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240104685
    Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ruijin Wu, Michael John Livesley, Kiia Kallio, Jan H. Achrenius, Mika Tuomi
  • Publication number: 20210398349
    Abstract: Some implementations provide systems, devices, and methods for rendering a plurality of primitives of a frame, the plurality of primitives being divided into a plurality of batches of primitives and the frame being divided into a plurality of bins. For at least one batch of the plurality of batches the rendering includes, for each of the plurality of bins, rendering primitives of a first sub-batch rasterizing to that bin, and for each of the plurality of bins, rendering primitives of a second sub-batch rasterizing to that bin.
    Type: Application
    Filed: September 25, 2020
    Publication date: December 23, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jan H. Achrenius, Kiia Kallio, Miikka Kangasluoma, Ruijin Wu, Anirudh R. Acharya
  • Patent number: 8698825
    Abstract: A system, method, and computer program product are provided for optimizing use of a vertex cache. In use, information is identified, where such information is associated with vertex data stored in a vertex cache. To this end, use of the vertex cache may be optimized utilizing the information. In one embodiment, the information may include new information derived from the vertex data, and optionally index data, prior to processing of the vertex data. Further, the vertex cache may optionally utilize the information to optimize performance of the vertex cache by minimizing a number of cache misses.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: April 15, 2014
    Assignee: NVIDIA Corporation
    Inventors: Tuomas J. Lukka, Tero T. Karras, Jan H. Achrenius