Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

Abstract: A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.

Abstract: A methodology for robust post-gate spacer processing that exhibits reduced variability and marginalities, and the resulting device are disclosed. Embodiments may include forming an oxide layer over a gate stack, forming a nitride layer over the oxide layer, partially removing the nitride layer to expose a portion of the oxide layer, forming a protective nitride layer directly over the partially exposed oxide layer and a remaining portion of the nitride layer, removing the protective nitride layer from the gate stack, and at least partially removing the remaining portion of the nitride layer.

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

Abstract: FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET.

Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

Abstract: Methods for forming a vertical capacitance structure and the resulting devices are disclosed. Embodiments may include forming fins on a substrate; conformally forming a first metal layer over the fins; conformally forming an insulation layer over the first metal layer; and forming a second metal layer over the insulation layer.

Abstract: Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract: A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space.

Abstract: Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region. The method deposits an interlayer dielectric material over the semiconductor substrate. Further, the method etches the interlayer dielectric material to form a hole defining an exposed portion of the source/drain region. The method includes forming a contact forming a contact in the hole over the exposed portion of the source/drain region and forming an interconnect in the hole over the contact.

Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.