Abstract: Circuitry is disclosed herein that dynamically (temperature-invariant and voltage-invariant) adjusts the Ron of switches in a resistive Nyquist-rate digital to analog converter (DAC) to thereby reduce DAC nonlinearity errors and improve INL results of greater than 16b. Consistent with the present disclosure, the DAC includes an R-2R ladder in which each bit corresponds to a switch. A control circuit is provided for generating signals applied to the gate of the switch to cause the on-resistances of the switch to be a particular value, such that the on-resistance of the switch plus the sum of two resistors, one having the resistance R, and the other having a resistance R? is equivalent to the resistance of the 2R-size resistors or twice the resistance of the R-sized resistors in the ladder.

Abstract: A high-voltage circuit has a protection circuit protecting a low-voltage MOSFET. A first MOSFET, a low-voltage device with a gate coupled to an input voltage, is coupled in a series with a second MOSFET which is a high-voltage device, both of a first conductivity type. A protection circuit includes a third, a fourth, and a fifth MOSFET. The third MOSFET has a second conductivity type and source and body coupled to the input voltage. The fourth MOSFET has the first conductivity type and a drain coupled to a drain of the third MOSFET, a gate coupled to a second bias voltage, and a source and a body coupled to the first power terminal. The fifth MOSFET has the first conductivity type and a drain coupled to the input voltage, a gate coupled to the drain of the fourth MOSFET, and a source coupled to the first power terminal.

Abstract: A high-voltage circuit has a protection circuit protecting a low-voltage MOSFET. A first MOSFET, a low-voltage device with a gate coupled to an input voltage, is coupled in a series with a second MOSFET which is a high-voltage device, both of a first conductivity type. A protection circuit includes a third, a fourth, and a fifth MOSFET. The third MOSFET has a second conductivity type and source and body coupled to the input voltage. The fourth MOSFET has the first conductivity type and a drain coupled to a drain of the third MOSFET, a gate coupled to a second bias voltage, and a source and a body coupled to the first power terminal. The fifth MOSFET has the first conductivity type and a drain coupled to the input voltage, a gate coupled to the drain of the fourth MOSFET, and a source coupled to the first power terminal.

Abstract: An output circuit for a class AB push-pull amplifier includes an upper cascode output stage and a lower cascode output stage. The upper cascode stage includes first and second PMOS transistors connected in series between a positive power supply node and an output node, the first PMOS transistor configured to receive a first complementary input signal. The lower cascode output stage includes first and second NMOS transistors connected in series between a negative power supply node and the output node, the first NMOS transistor configured to receive a second complementary input signal. The output circuit also includes a bias circuit configured for providing a first bias voltage to a gate node of the second NMOS transistor and a second bias voltage to a gate node of the second PMOS transistor, in which the first and the second bias voltages being substantially proportional to the output voltage.

Abstract: An output circuit for a class AB push-pull amplifier includes an upper cascode output stage and a lower cascode output stage. The upper cascode stage includes first and second PMOS transistors connected in series between a positive power supply node and an output node, the first PMOS transistor configured to receive a first complementary input signal. The lower cascode output stage includes first and second NMOS transistors connected in series between a negative power supply node and the output node, the first NMOS transistor configured to receive a second complementary input signal. The output circuit also includes a bias circuit configured for providing a first bias voltage to a gate node of the second NMOS transistor and a second bias voltage to a gate node of the second PMOS transistor, in which the first and the second bias voltages being substantially proportional to the output voltage.

Abstract: A PMOS device comprises a semiconductor-on-insulator (SOI) substrate having a layer of insulating material over which is provided an active layer of n-type semiconductor material. P-type source and drain regions are provided by diffusion in the n-type active layer. A p-type plug is provided at the source region, which extends through the active semiconductor layer to the insulating layer. The plug is provided so as to enable the source voltage applied to the device to be lifted significantly above the substrate voltage without the occurrence of excessive leakage currents.

Abstract: The invention relates to a power supply (9) for a deflection circuit (1), that comprises a deflection coil (2) for connection to a picture tube, a drive circuit (4,5,6) connected to the deflection coil (2), and a deflection controller (3) for controlling the drive circuit (4,5,6). According to the invention the power supply (9) comprises a first input (10,11) connection to an output of the drive circuit (4,5,6) and the deflection coil, a second input connected to a power source (Vinput), a power supply output (13) connected to the drive circuit (4,5,6), and an adapter for adapting the power supply (VP) to the output (13) from the second input (Vinput) dependent on the first input (10,11).

Abstract: The invention relates to a power supply (9) for a deflection circuit (1), that comprises a deflection coil (2) for connection to a picture tube, a drive circuit (4, 5, 6) connected to the deflection coil (2), and a deflection controller (3) for controlling the drive circuit (4, 5, 6). According to the invention the power supply (9) comprises a first input (10, 11) connected to an output of the drive circuit (4, 5, 6) and the deflection coil, a second input connected to a power source (Vinput) a power supply output (13) connected to the drive circuit (4, 5, 6), and an adapter for adapting the power supply (VP) to the output (13) from the second input (Vinput) dependent on the first input (10, 11).