Abstract: The invention provides a compact test sequence for testing integrated memories. First, all storage positions are filled with the bit "0". Subsequently, in a given order of the addresses, the "0" bit written for each address is read; immmediately thereafter a "1" bit is written in those bit positions. The positions are again tested by reading the "1" bits. When the last address of the predetermined order is reached, the "1" is read in the same order for each address. Subsequently a "0" is written, which is finally tested by reading again. When the last address is reached, all addresses are read in the reverse order, and a "1" is written, which is tested again. When the first address is reached, all addresses are read, filled with a "0" and tested. This process may be repeated as many times as there are bits in the address. The significance of the address bits are modified to form the predetermined order, for example, by cyclic rotation.