Abstract: It is described an electronic circuit chip for an RFID tag. The electronic circuit chip comprises (a) an access circuit configured for coupling the electronic circuit chip to an antenna element of the RFID tag, and (b) a memory device being connected to the access circuit. The memory device is configured for storing a secret value, for making retrievable the secret value, and for deleting the secret value. Deleting the secret value is accomplished if the secret value has been retrieved by means of a first attempt procedure for retrieving the stored secret value. It is further described an RFID tag comprising such an electronic circuit chip and a method for managing the use of a read-only-once secret value by an RFID tag with such an electronic circuit chip.

Abstract: A method of performing a secure function on data inputs by a security module, including: receiving an encrypted data value by the security module; decrypting the encrypted data value using a white-box decryption block cipher and encoding the decrypted data value, wherein the data value is invisible to an attacker; performing a function on the encoded data value and producing an encoded result of the function, wherein the data value and the result are invisible to the attacker; decoding the encoded result of the programmed function and then encrypting the result using a white-box encryption block cipher, wherein the result is invisible to the attacker.

Abstract: A method of performing a keyed cryptographic operation mapping an input message to an output message, wherein the input message comprises m input data and the output message comprises m output data and wherein the cryptographic operation includes at least one round and the cryptographic operation specifies a substitution box for mapping input data into output data, including: transforming each of the m input data into n output data using n split substitution boxes, wherein the n split substitution boxes sum to the specified substitution box; and mixing and combining the m×n output data.

Abstract: This invention provides a clock control circuit, which can be added to any pipeline-processor to solve timing problems arising from variations due to process outcome and environmental conditions. Critical instructions are detected (instructions that exercise critical paths) in conjunction with environmental sensing (such as process, temperature and voltage). This information is used to control cycle stealing.

Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.

Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.

Abstract: A circuit and a method are used estimate quality of the output of a wireless receiver. This quality measure is used to control the supply voltage and thereby provide power savings.

Abstract: A circuit and a method are used estimate quality of the output of a wireless receiver. This quality measure is used to control the supply voltage and thereby provide power savings.

Abstract: A multiprocessor system has a background memory and a plurality of processing elements, each comprising a processor core and a cache circuit. The processor cores execute programs of instructions and the cache circuits cache background memory data accessed by the programs. A write back monitor circuit is used to buffer write addresses used for writing data by at least part of the processor cores. The programs contain commands to read the buffered write back addresses from the write back monitor circuit and commands from the programs to invalidate cached data for the write back addresses read by the commands to read the buffered write back addresses. Thus cache management is performed partly by hardware and partly by the program that uses the cache. The processing core may be a VLIW core, in which case instruction slots that are not used by the program can be made useful to include instructions for cache management.

Abstract: A multi-threaded processor comprises a processing unit (PU) for concurrently processing multiple threads. A register file means (RF) is provided having a plurality of registers, wherein a first register (LI) is used for storing loop invariant values and N second registers (LVI-LVN) are each used for storing loop variant values. Furthermore N program counters (PCI-PCN) are provided each being associated to one of the multiple threads, wherein N being the number of threads being processed.

Abstract: Various embodiments relate to an anti-tampering circuit for a secure device including: a signal delay detector; a clock delay detector; a clock duty cycle detector; and a protection unit that receives an error indication from the signal delay detector, clock delay detector, and the clock duty cycle detector, wherein the protection unit indicates tampering to a secure device upon receiving the error indication.

Abstract: Various exemplary embodiments relate to a method and related motion estimation unit for performing motion estimation on video data comprising a plurality of frames. The method may begin by reading a current frame of the plurality of frames from a memory of a motion estimation unit. The method may then select a motion vector for each respective block of pixels in a current row of the current frame. The step of selecting the motion vector may include, for each respective block, selecting, by the motion estimation unit, a candidate vector for at least one block directly surrounding the respective block based on a determination of whether the directly surrounding block has been processed for the current frame, calculating, for each candidate vector, a difference value, and selecting, as the motion vector, the candidate vector with the lowest difference value.

Abstract: A processing circuit has functional units (10a-c) configured to perform operations each in response to a respective command. The functional units (10a-c) are configured to execute at least one of the operations with a selectable level of susceptibility to incurring an error during execution. Different functional units may be provided, designed to execute the same operation with different levels of susceptibility at the cost of more circuit area, power consumption or execution time in the case of less susceptibility. The less susceptible functional unit may comprise additional error correction circuits, or more pipeline stages for example. The program directs commands to execute the operation to different functional units according to the required level of susceptibility. High level programs may be provided wherein variables are declared with a specified level of reliability. These declarations may be used during compilation to select how instructions will be executed.

Abstract: A computer processor 100 is provided which hides jump instructions, in particular condition jump instructions, from side-channels. The processor comprises a forward jump detector 254 for detecting a forward jump instruction having a jump target location which lies ahead and a jump inhibitor 262 for inhibiting an execution of the forward jump instruction. The computer processor is configured for executing at least one intermediate computer instruction located between the inhibited forward jump instruction and the jump target location. The processor further comprises a storage destination modifier 260, 262 for modifying the storage destination determined by the at least one intermediate computer instruction to suppress the effects of execution of intermediate instructions. Since the intermediate instruction is executed regardless of the forward jump instruction, the jump is hidden in a side-channel. Secret information, such as cryptographic keys, on which the forward jump may depend, is also hidden.

Abstract: A circuit that comprises a processor core (100), a background memory (12) and a cache circuit (102) between the processor core (100) and the background memory (12). In operation a sub-range of a plurality of successive addresses is detected within a range of successive addresses associated with a cache line, the sub-range containing addresses for which updated data is available in the cache circuit. Updated data for the sub-range is selectively transmitted to the background memory (12). A single memory transaction for a series of successive addresses may be used, the detected sub-range being used to set the start address and a length or end address of the memory transaction. This may be applied for example when only updated data is available in the cache line, and no valid data for other addresses, or to reduce bandwidth use when only a small run of addresses has been updated in the cache line.

Abstract: A multiprocessor system has a background memory and a plurality of processing elements (10), each comprising a processor core (100) and a cache circuit (102). The processor cores (100) execute programs of instructions and the cache circuits (102) cache background memory data accessed by the programs. A write back monitor circuit (14) is used to buffer write addresses used for writing data by at least part of the processor cores (100). The programs contain commands to read the buffered write back addresses from the write back monitor circuit (14) and commands from the programs to invalidate cached data for the write back addresses read by the commands to read the buffered write back addresses. Thus cache management is performed partly by hardware and partly by the program that uses the cache. The processing core may be a VLIW core, in which case instruction slots that are not used by the program can be made useful to include instructions for cache management.

Abstract: Data is processed using a first and second processing circuit (12) coupled to a background memory (10) via a first and second cache circuit (14, 14?) respectively. Each cache circuit (14, 14?) stores cache lines, state information defining states of the stored cache lines, and flag information for respective addressable locations within at least one stored cache line. The cache control circuit of the first cache circuit (14) is configured to selectively set the flag information for part of the addressable locations within the at least one stored cache line to a valid state when the first processing circuit (12) writes data to said part of the locations, without prior loading of the at least one stored cache line from the background memory (10). Data is copied from the at least one cache line into the second cache circuit (14?) from the first cache circuit (14) in combination with the flag information for the locations within the at least one cache line.

Abstract: A processing circuit has functional units (10a-c) configured to perform operations each in response to a respective command. The functional units (10a-c) are configured to execute at least one of the operations with a selectable level of susceptibility to incurring an error during execution. Different functional units may be provided, designed to execute the same operation with different levels of susceptibility at the cost of more circuit area, power consumption or execution time in the case of less susceptibility. The less susceptible functional unit may comprise additional error correction circuits, or more pipeline stages for example. The program directs commands to execute the operation to different functional units according to the required level of susceptibility. High level programs may be provided wherein variables are declared with a specified level of reliability. These declarations may be used during compilation to select how instructions will be executed.

Abstract: Various exemplary embodiments relate to a method and related motion estimation unit for performing motion estimation on video data comprising a plurality of frames. The method may begin by reading a current frame of the plurality of frames from a memory of a motion estimation unit. The method may then select a motion vector for each respective block of pixels in a current row of the current frame. The step of selecting the motion vector may include, for each respective block, selecting, by the motion estimation unit, a candidate vector for at least one block directly surrounding the respective block based on a determination of whether the directly surrounding block has been processed for the current frame, calculating, for each candidate vector, a difference value, and selecting, as the motion vector, the candidate vector with the lowest difference value.

Abstract: A data processing device has a configurable functional unit for executing an instruction according to a configurable function. The configurable functional unit has a plurality of independent configurable logic blocks for performing programmable logic operations to implement the configurable function. Configurable connection circuits are provided between the configurable logic blocks and both the inputs and the outputs of the configurable functional unit. This allows an optimalization of the distribution of logic functions over the configurable logic blocks.