Patents by Inventor Jan-Hun Tsai

Jan-Hun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to design and verify an integrated circuit device with multiple power domains
    Patent number: 7103862
    Abstract: A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: September 5, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Nai-Yin Sung, Hsing-Chien Huang, Jan-Hun Tsai
  • Method to design and verify an integrated circuit device with multiple power domains
    Publication number: 20050216872
    Abstract: A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.
    Type: Application
    Filed: March 23, 2004
    Publication date: September 29, 2005
    Inventors: Nai-Yin Sung, Hsing-Chien Huang, Jan-Hun Tsai