Abstract: A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region.

Abstract: A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region.

Abstract: A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region.

Abstract: A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second primary opposed surfaces and an aperture formed therebetween. A flexible thin film interconnect structure having bottom and top opposing surfaces is formed over the first primary surface of the metal substrate and over the aperture such that a first region of the bottom surface is in direct contact with the first surface of the metal substrate and a second region of the bottom surface is opposite the aperture. Within the second region of the bottom surface are a first plurality of exposed bonding pads having a first pitch appropriate for attaching the integrated circuit die to package. The top surface of the flexible thin film interconnect structure includes a second plurality of exposed bonding pads having a pitch greater than the first pitch.

Abstract: The present invention provides a solution to the problem of controlling the inter-layer impedance of a deposited thin film layer stack accommodating high-density interconnects. The invention enables high-density signal lines to be routed over a reference plane to achieve a desired characteristic impedance. In one embodiment, a first thin-film metal layer is formed on a planarized layer fabricated from multiple thin film dielectric layers. The reduced pad footprint in the first thin-film metal layer allows a major portion of the first thin-film metal layer to serve as a reference, or ground, plane to signal lines formed in a second thin-film metal layer that is separated from the first thin-film metal layer by a thin dielectric layer.

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract: The present invention provides a solution to the problem of controlling the inter-layer impedance of a deposited thin film layer stack accommodating high-density interconnects. The invention enables high-density signal lines to be routed over a reference plane to achieve a desired characteristic impedance. In one embodiment, a first thin-film metal layer is formed on a planarized layer fabricated from multiple thin film dielectric layers. The reduced pad footprint in the first thin-film metal layer allows a major portion of the first thin-film metal layer to serve as a reference, or ground, plane to signal lines formed in a second thin-film metal layer that is separated from the first thin-film metal layer by a thin dielectric layer.

Abstract: The present invention provides a method for controlling the mechanical stresses at the interfaces of the metal and dielectric materials in the printed wiring substrates of high density interconnects. The invention enables the minimization of cracking due to these stresses and does so in an economically attractive process that is able to meet the needs of today's high density interconnect applications. In one embodiment, the method of the present invention dispenses mechanical stresses in a high density interconnect printed wiring board substrate having a first patterned conductive layer formed over an upper surface of the substrate. The patterned conductive layer includes multiple conductive lines each having edges that define the boundaries of the conductive lines. The method of the invention forms a composite dielectric layer over the first patterned conductive layer and between the edges of the conductive layer.

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract: Low-impedance high density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract: A method for forming a high density interconnect printed wiring board substrate that has a first patterned conductive layer formed over an upper surface of the substrate that includes multiple conductive lines having edges that define the boundaries of the conductive lines and a dielectric layer formed over the patterned conductive layer and between the edges of the conductive lines. The method includes forming a thin film conductive layer over the dielectric layer, and patterning the thin film conductive layer such that, after the patterning step, the thin film conductive layer overlies each of the edges of the conductive lines. In a preferred embodiment, the thin film conductive layer is patterned such that, after the patterning step, the layer overlies the edges of the conductive lines by at least 10 microns. In another aspect of the invention, a method for strengthening thin film build-up layers deposited over a high density interconnect common circuit base is taught.

Abstract: A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer.