Patents by Inventor Jan Krajniak
Jan Krajniak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887962Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: GrantFiled: June 16, 2020Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Sairam Agraharam, Edvin Cetegen, Anurag Tripathi, Malavarayan Sankarasubramanian, Jan Krajniak, Manish Dubey, Jinhe Liu, Wei Li, Jingyi Huang
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Patent number: 11574851Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 27, 2019Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Patent number: 11545407Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.Type: GrantFiled: January 10, 2019Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
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Publication number: 20210391295Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Sairam Agraharam, Edvin Cetegen, Anurag Tripathi, Malavarayan Sankarasubramanian, Jan Krajniak, Manish Dubey, Jinhe Liu, Wei Li, Jingyi Huang
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Publication number: 20200273811Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Debendra Mallik, Mitul Modi, Sanka Ganesan, Edvin Cetegen, Omkar Karhade, Ravindranath Mahajan, James C. Matayabas, Jr., Jan Krajniak, Kumar Singh, Aastha Uppal
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Publication number: 20200273768Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Publication number: 20200273772Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Publication number: 20200227332Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.Type: ApplicationFiled: January 10, 2019Publication date: July 16, 2020Applicant: Intel CorporationInventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, JR.
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Publication number: 20180324955Abstract: An apparatus is described. The apparatus includes a first planar board to second planar board interface. The first planar board to second planar board interface includes a reflowed solder electrical connection structure between the first and second boards and a no flow adhesive. The reflowed solder electrical connection structure includes a reflowed solder ball and a reflowed tinned pad.Type: ApplicationFiled: December 23, 2015Publication date: November 8, 2018Inventors: Mohit SOOD, Huili XU, Wei TAN, Suriyakala RAMALINGAM, Jan KRAJNIAK, Nish ANANTHAKRISHNAN
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Publication number: 20180068926Abstract: Embodiments of the present disclosure describe an energy storage material for thermal management and associated techniques and configurations. In one embodiment, an energy storage material may include an organic matrix and a solid-solid phase change material dispersed in the organic matrix, the solid-solid phase change material to change crystalline structure and absorb heat while remaining a solid at a threshold temperature associated with operation of an integrated circuit (IC) die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 27, 2015Publication date: March 8, 2018Inventors: JAN KRAJNIAK, TANNAZ HARIRCHIAN, KELLY P. LOFGREEN, JAMES C. MATAYABAS, Jr., NACHIKET R. RARAVIKAR, ROBERT L. SANKMAN
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Publication number: 20170053858Abstract: Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 20, 2015Publication date: February 23, 2017Inventors: Jan Krajniak, Carl L. Deppisch, Kabirkumar J. Mirpuri, Hongjin Jiang, Fay Hua, Yuying Wei, Beverly J. Canham, Jiongxin Lu, Mukul P. Renavikar