Abstract: Storing data in a distributed database management system. The distributed database management system includes a first set of database tables, wherein data of a logical database table is distributed among the first set of database tables according to a first distribution key. A second set of database tables is maintained using a second distribution key that is different from the first distribution key. Furthermore, at least one performance metric value for the stored query when executing a query is maintained, and the second distribution key is determined based on the at least one performance metric value.

Abstract: A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica.

Abstract: A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica.

Abstract: Storing data in a distributed database management system. The distributed database management system includes a first set of database tables, wherein data of a logical database table is distributed among the first set of database tables according to a first distribution key. A second set of database tables is maintained using a second distribution key that is different from the first distribution key. Furthermore, at least one performance metric value for the stored query when executing a query is maintained, and the second distribution key is determined based on the at least one performance metric value.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica.

Abstract: A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: A system and method is provided for updating a hash tree in a protected environment. An integrity protection controller is provided for observing one or more system parameters of a storage system and one or more hash tree parameters of the hash trees, and for updating a hash tree in dependence on the storage system parameter and the hash tree parameter.

Abstract: A system and associated method for block ciphering. The method generates a key that is specific to a text block being encrypted and later being decrypted. The text block is encrypted by a block cipher encryption with the key. The encrypted text block is decrypted by a block cipher decryption with the key back to the text block. Altering a single bit in either the encrypted text block or the key results in unsuccessful decryption such that a decrypted text block is completely different from the before encryption.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: A system and associated method for block ciphering. The method generates a key that is specific to a text block being encrypted and later being decrypted. The text block is encrypted by a block cipher encryption with the key. The encrypted text block is decrypted by a block cipher decryption with the key back to the text block. Altering a single bit in either the encrypted text block or the key results in unsuccessful decryption such that a decrypted text block is completely different from the before encryption.

Abstract: A system and method is provided for updating a hash tree in a protected environment. An integrity protection controller is provided for observing one or more system parameters of a storage system and one or more hash tree parameters of the hash trees, and for updating a hash tree in dependence on the storage system parameter and the hash tree parameter.