Abstract: A semiconductor device includes a first under-bump metallization (UBM) layer disposed over a bond pad, a dielectric layer above an interconnect layer having a via exposing at least a portion of the first UBM layer. A second UBM layer is disposed above the first UBM layer and forms a UBM bucket over the via. The first UBM layer and UBM bucket are configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

Abstract: A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a first inverter comprising a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a second inverter comprising a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the second node being coupled to a control terminal of the second transistor. The memory array further comprises a third inverter and a fourth inverter.

Abstract: A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein the diffusion material is electrically isolated from the substrate layer by at least one p-n junction. The fuse structure can include a cathode comprising conductive material overlaying the diffusion material. The fuse structure further can include a fuse link comprising conductive material overlaying the diffusion material, wherein a first end of the fuse link couples to the anode and a second end of the fuse link, that is distal to the first end, couples to the cathode.

Abstract: An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract: A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; and a second inverter having a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the first node being coupled to control terminals of the third transistor and the fourth transistor and the second node being coupled to control the first transistor and the second transistor; wherein the third transistor is implemented with physical dimensions which make the third transistor stronger than the first transistor, or the second transistor is implemented with physical dimensions which make the second transistor stronger than the fourth transistor.

Abstract: A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.

Abstract: A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.

Abstract: A method and apparatus compensate for process variations in the fabrication of semiconductor devices. A semiconductor device includes a control circuit that measures a performance parameter of the device, and in response thereto selectively biases one or more well regions of the device to compensate for process variations. For some embodiments, if measurement of the performance parameter indicates that the device does not fall within a specified range of operating parameters, the control circuit biases selected well regions to sufficiently alter the operating characteristics of transistors formed therein so that the device falls within the specified range of operating parameters.

Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Abstract: Various embodiments of the present invention describe circuits for and methods of detecting a defect in a component formed in a substrate of an integrated circuit. According to one embodiment, a circuit comprises a plurality of components formed in a substrate and coupled in series by a plurality of signal paths extending from a first end to a second end. An input signal coupled to the first end of the first signal path is detected a signal detector coupled to a second end of the first signal path to determine whether there is a defect in a component formed in the substrate. Switching networks at the inputs and the outputs of the plurality signal paths enable determining a particular signal path that had a defect. Alternate embodiments describe circuits for determining the location of a defective component in a signal path. Various methods of detecting defective components are also described.

Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

Abstract: Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes and corrupt the data state of the memory cell. Separating the half cells by at least two rows avoids corruption that could occur if diagonally arranged half cells were hit by a high-energy particle. In a particular embodiment, offset half cells are used at the top and bottom, respectively, of two adjacent columns of memory half cells.

Abstract: Methods of implementing a static memory cell compliant with the requirements of phase shift masks. A phase shift compliant memory cell is generated by implementing a single bit line, two word lines, first and second cross-coupled logic gates, and first and second pass gates. The logic gates and pass gates include transistors that use a fabrication layer (e.g., polysilicon) to implement the gate nodes of the transistors. All of these gate nodes extend substantially in a first direction. Throughout the static memory cell, the fabrication layer is implemented without T-shaped polygons in compliance with the requirements for a phase shift mask. In some embodiments, the static memory cell is a configuration memory cell for a PLD, and the method includes implementing an interconnection between at least one of the first and second storage nodes and programmable logic elements of the PLD.

Abstract: Static memory cell circuits having a single bit line further include first and second word lines, first and second cross-coupled logic gates, and first and second pass gates. The first pass gate is coupled between the bit line and a first storage node at the output of the first logic gate, and has a gate terminal coupled to the first word line. The second pass gate is coupled between the bit line and a second storage node at the output of the second logic gate, and has a gate terminal coupled to the second word line. The bit line and one of the word lines can be used to selectively set or reset a given static memory cell, if desired, without affecting other memory cells along the word line. In some embodiments, the static memory cell is a configuration memory cell of a programmable logic device (PLD).

Abstract: An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a gate-source coupled MOS transistor. If the MOS transistor is unprogrammed, then the resistive element ensures that the programmable transistor is turned off during read operations. However, when a programming voltage is applied across the source and drain terminals of the programmable transistor, the resistive element allows the programming voltage to be capacitively coupled to the gate of the programmable transistor from its drain. This turns the programmable transistor on, thereby reducing the snapback voltage of the programmable transistor, and hence, the required programming voltage. Once the snapback mode is entered, current flow through the programmable transistor increases until thermal breakdown occurs and the programmable transistor shorts out.

Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Abstract: For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

Abstract: A test circuit is included in an IC wafer for testing the reliability of ICS under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

Abstract: A method of testing reliability in an integrated circuit including an array of test circuits, each test circuit including a resistor. The method includes selecting a first test circuit from the array, measuring a pre-stress resistance value for the resistor in the selected test circuit, applying a high stress current across the resistor, removing the high stress current, and measuring a post-stress resistance value for the resistor. Other embodiments include measuring additional resistance values before applying and after removing the high stress current. One embodiment includes applying a positive voltage to one stress input terminal, and then testing a short sensing terminal for the positive voltage, both before and after applying the high stress current. These steps test for whether or not the high stress current has created a short in the test circuit.