Patents by Inventor Jan-Michael Stevenson

Jan-Michael Stevenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9698800
    Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 4, 2017
    Assignee: Linear Technology Corporation
    Inventor: Jan-Michael Stevenson
  • Patent number: 9397668
    Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 19, 2016
    Assignee: Linear Technology Corporation
    Inventors: Eric Wright Mumper, Jan-Michael Stevenson
  • Publication number: 20160182056
    Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Eric Wright Mumper, Jan-Michael Stevenson
  • Publication number: 20160036455
    Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).
    Type: Application
    Filed: March 17, 2015
    Publication date: February 4, 2016
    Inventor: JAN-MICHAEL STEVENSON
  • Patent number: 8610442
    Abstract: A method for detecting capacitor variation in a device comprises operating an oscillator in the device, the oscillator being an Inductive-Capacitive (LC) oscillator and including an inductor of known value and a capacitor under test, comparing an output of the oscillator to a reference output, and evaluating variation for a plurality of capacitors in the device based on the comparing.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: December 17, 2013
    Assignee: CSR Technology Inc.
    Inventors: Jan-Michael Stevenson, Timothy M. Magnusen
  • Patent number: 8586461
    Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: November 19, 2013
    Assignee: CSR Technology Inc.
    Inventor: Jan-Michael Stevenson
  • Patent number: 8421547
    Abstract: When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: April 16, 2013
    Assignee: CSR Technology Inc.
    Inventors: Michael Womac, Jan-Michael Stevenson
  • Patent number: 8351887
    Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: January 8, 2013
    Assignee: CSR Technology, Inc.
    Inventor: Jan-Michael Stevenson
  • Patent number: 8279101
    Abstract: High conversion rates are achieved in an analog to digital converter by tailoring the substrate type to specific operational elements of the converter. Embodiments place sample and hold processing circuitry on a substrate type having properties that allow for faster processing at high sampling/clock frequencies. Other operational elements of the converter are constructed on at least one other substrate type in keeping with the remainder of the circuitry for which the converter is being implemented. The sample and hold substrate may be implemented on any material which is capable of faster processing, such as silicon germanium, gallium arsenide, silicon bipolar, BiCMOS, and the like. Other portions may be implemented on a more CMOS substrate. Such systems and methods are able to implement analog-to digital conversion for broadband signals at high speeds without the need for extensive timing compensation, while also avoiding problems due to noise from further digital processing circuitry.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: October 2, 2012
    Assignee: CSR Technology Inc.
    Inventor: Jan-Michael Stevenson
  • Publication number: 20110285476
    Abstract: When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 24, 2011
    Applicant: Microtune (Texas), L.P.
    Inventors: Michael Womac, Jan-Michael Stevenson
  • Patent number: 7978011
    Abstract: Systems and methods which implement degeneration circuitry in a single-ended amplifier circuit to mitigate distortion associated with one or more amplifier components are disclosed. A degeneration circuit of embodiments adds an impedance to cancel the second-order distortion of an amplifier transistor of a single-ended amplifier circuit. A bias circuit may be provided to minimize bias offset between an amplifier transistor and a corresponding degeneration transistor.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: July 12, 2011
    Assignee: Zoran Corporation
    Inventor: Jan-Michael Stevenson
  • Publication number: 20110134334
    Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Applicant: Microtune, Inc.
    Inventor: Jan-Michael Stevenson
  • Publication number: 20110133833
    Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Applicant: Microtune, Inc.
    Inventor: Jan-Michael Stevenson
  • Publication number: 20110025396
    Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.
    Type: Application
    Filed: October 13, 2010
    Publication date: February 3, 2011
    Applicant: Microtune (Texas), L.P.
    Inventor: Jan-Michael Stevenson
  • Patent number: 7853227
    Abstract: A system for providing automatic gain control (AGC) comprises a signal path with an RF input, a plurality of power detectors in communication with the signal path, each of the power detectors operable to measure a total broadband power level of a signal in the signal path, each of the power detectors positioned to monitor a point in the signal path corresponding to a change in signal bandwidth, a control system operable to receive from each of the power detectors information associated with the power level and to adjust attenuation in the signal path in response to the information to achieve desired gain control.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: December 14, 2010
    Assignee: Microtune (Texas), L.P.
    Inventors: Jan-Michael Stevenson, Jose L. Esquivel, Carey Ritchey, Kim E. Beumer
  • Patent number: 7636559
    Abstract: A system for processing a signal comprises a Radio Frequency (RF) signal tuner, one or more filters in a signal path of the RF tuner each based on Inductive/Capacitive (LC) circuitry, a variation unit operable to measure a variation of the LC circuitry, and a frequency control unit adapted to adjust the one or more filters based on the LC variation during operation of the tuner.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: December 22, 2009
    Assignee: Microtune (Texas), L.P.
    Inventors: Timothy M. Magnusen, Jan-Michael Stevenson
  • Patent number: 7634243
    Abstract: Disclosed are systems and methods which utilize a relatively low cost first IF filter in a dual conversion tuner circuit. A preferred embodiment first IF filter is provided using a filter arrangement having a relatively high tolerance. Accordingly, preferred embodiment systems are designed such that they can accommodate the range of first IF frequencies that the large tolerance filter may provide. One aspect of this accommodation may include providing a means by which the system may detect the location of the passband of the IF filter in the spectrum. Another aspect of the accommodation for the range of first IF frequencies may include adjusting the first IF frequency utilized by the dual conversion tuner to match the passband of the IF filter. Additionally or alternatively, the passband of the first IF filter itself may be tuned, such as to provide a passband more near a desired IF frequency.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: December 15, 2009
    Assignee: Microtune (Texas), L.P.
    Inventors: Jose L. Esquivel, R. William Ezell, Jan-Michael Stevenson
  • Patent number: 7619421
    Abstract: A method for detecting capacitor variation in a device comprises operating an oscillator in the device, the oscillator being an Inductive-Capacitive (LC) oscillator and including an inductor of known value and a capacitor under test, comparing an output of the oscillator to a reference output, and evaluating variation for a plurality of capacitors in the device based on the comparing.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: November 17, 2009
    Assignee: Microtune (Texas), L.P.
    Inventors: Jan-Michael Stevenson, Timothy M. Magnusen
  • Publication number: 20090189619
    Abstract: A method for detecting capacitor variation in a device comprises operating an oscillator in the device, the oscillator being an Inductive-Capacitive (LC) oscillator and including an inductor of known value and a capacitor under test, comparing an output of the oscillator to a reference output, and evaluating variation for a plurality of capacitors in the device based on the comparing.
    Type: Application
    Filed: April 6, 2009
    Publication date: July 30, 2009
    Applicant: Microtune (Texas), L.P.
    Inventors: Jan-Michael Stevenson, Timothy M. Magnusen
  • Publication number: 20090167403
    Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 2, 2009
    Applicant: Microtune (Texas), L.P.
    Inventor: Jan-Michael Stevenson