Abstract: The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Abstract: The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

Abstract: A method for detecting capacitor variation in a device comprises operating an oscillator in the device, the oscillator being an Inductive-Capacitive (LC) oscillator and including an inductor of known value and a capacitor under test, comparing an output of the oscillator to a reference output, and evaluating variation for a plurality of capacitors in the device based on the comparing.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: High conversion rates are achieved in an analog to digital converter by tailoring the substrate type to specific operational elements of the converter. Embodiments place sample and hold processing circuitry on a substrate type having properties that allow for faster processing at high sampling/clock frequencies. Other operational elements of the converter are constructed on at least one other substrate type in keeping with the remainder of the circuitry for which the converter is being implemented. The sample and hold substrate may be implemented on any material which is capable of faster processing, such as silicon germanium, gallium arsenide, silicon bipolar, BiCMOS, and the like. Other portions may be implemented on a more CMOS substrate. Such systems and methods are able to implement analog-to digital conversion for broadband signals at high speeds without the need for extensive timing compensation, while also avoiding problems due to noise from further digital processing circuitry.

Abstract: When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.

Abstract: Systems and methods which implement degeneration circuitry in a single-ended amplifier circuit to mitigate distortion associated with one or more amplifier components are disclosed. A degeneration circuit of embodiments adds an impedance to cancel the second-order distortion of an amplifier transistor of a single-ended amplifier circuit. A bias circuit may be provided to minimize bias offset between an amplifier transistor and a corresponding degeneration transistor.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.

Abstract: A system for providing automatic gain control (AGC) comprises a signal path with an RF input, a plurality of power detectors in communication with the signal path, each of the power detectors operable to measure a total broadband power level of a signal in the signal path, each of the power detectors positioned to monitor a point in the signal path corresponding to a change in signal bandwidth, a control system operable to receive from each of the power detectors information associated with the power level and to adjust attenuation in the signal path in response to the information to achieve desired gain control.

Abstract: A system for processing a signal comprises a Radio Frequency (RF) signal tuner, one or more filters in a signal path of the RF tuner each based on Inductive/Capacitive (LC) circuitry, a variation unit operable to measure a variation of the LC circuitry, and a frequency control unit adapted to adjust the one or more filters based on the LC variation during operation of the tuner.

Abstract: Disclosed are systems and methods which utilize a relatively low cost first IF filter in a dual conversion tuner circuit. A preferred embodiment first IF filter is provided using a filter arrangement having a relatively high tolerance. Accordingly, preferred embodiment systems are designed such that they can accommodate the range of first IF frequencies that the large tolerance filter may provide. One aspect of this accommodation may include providing a means by which the system may detect the location of the passband of the IF filter in the spectrum. Another aspect of the accommodation for the range of first IF frequencies may include adjusting the first IF frequency utilized by the dual conversion tuner to match the passband of the IF filter. Additionally or alternatively, the passband of the first IF filter itself may be tuned, such as to provide a passband more near a desired IF frequency.

Abstract: A method for detecting capacitor variation in a device comprises operating an oscillator in the device, the oscillator being an Inductive-Capacitive (LC) oscillator and including an inductor of known value and a capacitor under test, comparing an output of the oscillator to a reference output, and evaluating variation for a plurality of capacitors in the device based on the comparing.