Abstract: In a pipeline data processing system, a method for additively converting an address expressed in offset form to a corresponding real address in main memory (assuming that such address exists in main memory). Because of the pipeline data processing design, this offset address can be accessed from main memory in the same amount of time required by a non-offset, real address. An apparatus for practicing this method is also provided. This method and apparatus will perform the functions usually performed by a translation table or similar device in virtual memory systems. Furthermore, it will perform those functions faster and will utilize a smaller integrated circuit area than translation table type virtual memory systems.