Patents by Inventor Jan Paul Antonie van der Wagt

Jan Paul Antonie van der Wagt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12041713
    Abstract: An example method performed for a circuit path includes: receiving signals in the circuit path; and controlling states of the signals in the circuit path based on skews produced by circuits electrically connected in series in the circuit path. The states are controlled by inverting or not inverting the signals in the circuit path so that skews produced by different circuits in the circuit paths at least partially cancel.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 16, 2024
    Assignee: TERADYNE, INC.
    Inventors: Jan Paul Antonie van der Wagt, Bradley A. Phillips
  • Patent number: 10996272
    Abstract: An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 4, 2021
    Assignee: TERADYNE, INC.
    Inventor: Jan Paul Antonie van der Wagt
  • Patent number: 10276229
    Abstract: Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edge of a version of a signal to provide a predefined logic level at the latch output; a first delay circuit that is controllable to configure a first delay, the first delay circuit being electrically connected to the first latch input and being for adjusting a rise portion of a skew in a first version of the signal; and a second delay circuit that is controllable to configure a second delay, the second delay circuit being electrically connected to the second latch input and being for adjusting a fall portion of the skew in a second version the signal.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Teradyne, Inc.
    Inventor: Jan Paul Antonie van der Wagt
  • Publication number: 20190066757
    Abstract: Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edge of a version of a signal to provide a predefined logic level at the latch output; a first delay circuit that is controllable to configure a first delay, the first delay circuit being electrically connected to the first latch input and being for adjusting a rise portion of a skew in a first version of the signal; and a second delay circuit that is controllable to configure a second delay, the second delay circuit being electrically connected to the second latch input and being for adjusting a fall portion of the skew in a second version the signal.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventor: Jan Paul Antonie van der Wagt
  • Publication number: 20190069394
    Abstract: An example method performed for a circuit path includes: receiving signals in the circuit path; and controlling states of the signals in the circuit path based on skews produced by circuits electrically connected in series in the circuit path. The states are controlled by inverting or not inverting the signals in the circuit path so that skews produced by different circuits in the circuit paths at least partially cancel.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Jan Paul Antonie van der Wagt, Bradley A. Phillips
  • Patent number: 9503065
    Abstract: Example circuitry includes: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, where the first clock signal is calibrated to compensate for a first timing error in a rising edge of the data; a second sampling circuit configured to operate based on a second clock signal, to receive the data, and to sample the data, where the second first clock signal is calibrated to compensate for a second timing error in a falling edge of the data; and a third sampling circuit to receive the data and a third clock signal, to sample the data based on the third clock signal to produce sampled data, and to control an output of the circuitry based on the sampled data to be either an output of the first sampling circuit or an output of the second sampling circuit.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 22, 2016
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Antonie van der Wagt, Ron Sartschev, Bradley A Phillips
  • Publication number: 20160065183
    Abstract: An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 3, 2016
    Inventor: Jan Paul Antonie van der Wagt