Patents by Inventor Jan Roelof Westra
Jan Roelof Westra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063807Abstract: Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and/or calibration based on signal measurements taken at the output stage of a device comprising the DAC.Type: ApplicationFiled: September 30, 2023Publication date: February 22, 2024Inventors: Jan Roelof Westra, Mohammadreza Mehrpoo, Frank van der Goes
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Publication number: 20230353184Abstract: In some aspects, the disclosure is directed to methods and systems for one or more line-drivers configured to selectively operate between a plurality of modes. When operating as a voltage-mode line-driver increased power efficiency may be realized. When operating as a current-mode line-driver, an increased transmission power may be realized. When operating in a dual/additive mode, still further increased transmission power may be realized.Type: ApplicationFiled: April 21, 2023Publication date: November 2, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventors: Jan Mulder, Xiaodong Liu, Mohammadreza Mehrpoo, Jan Roelof Westra
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Patent number: 10903641Abstract: A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.Type: GrantFiled: April 17, 2018Date of Patent: January 26, 2021Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Jan Roelof Westra, Jan Mulder
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Publication number: 20190319444Abstract: A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.Type: ApplicationFiled: April 17, 2018Publication date: October 17, 2019Inventors: Jan Roelof WESTRA, Jan MULDER
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Patent number: 10250338Abstract: An apparatus includes a transmitter circuit coupled to a termination resistor. The transmitter circuit generates a number of link pulses. A driver circuit is coupled to the transmitter circuit to control a dynamic range of the link pulses. A transformer couples the termination resistor via a transmission medium to a far-end transceiver. The driver circuit controls the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and the complementary digital input signals include ramp sections.Type: GrantFiled: April 24, 2018Date of Patent: April 2, 2019Assignee: Avago Technologies International Sales PTE. LimitedInventors: Jan Roelof Westra, Jan Mulder
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Patent number: 9543752Abstract: A device for digitally protecting against an overvoltage event may include a front-end circuit, an overvoltage protection circuit, and a protection switch. The protection switch may be coupled to the overvoltage protection circuit and may be configured to decouple the front-end circuit from an external medium, in response to a clamp signal. The overvoltage protection circuit may be configured to detect the overvoltage event at one or more nodes of a circuit. In response to the detection of the overvoltage event, the overvoltage protection circuit may generate the clamp signal to activate the protection switch.Type: GrantFiled: September 30, 2013Date of Patent: January 10, 2017Assignee: Broadcom CorporationInventors: Jan Roelof Westra, Jan Mulder, Qiongna Zhang, Jeffrey Allan Riley, Davide Vecchi
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Patent number: 9031177Abstract: A receiver is disclosed that is capable of correcting for harmonic distortion injected into received analog signals. The receiver splits the analog signal in the analog front-end and modifies the split analog signals with a difference signal. After amplification and/or sampling, the modified analog signals are recombined in a main data pathway and are kept separate in a secondary pathway. Utilizing the difference signal, a feedback loop that includes distorters and an LMS filter detects the distortion coefficient of the harmonic distortion. A distorter in the main data pathway utilizes the detected distortion coefficient to correct the harmonic distortion in the analog signal.Type: GrantFiled: December 20, 2012Date of Patent: May 12, 2015Assignee: Broadcom CorporationInventors: Frank van der Goes, Jan Roelof Westra
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Publication number: 20150085412Abstract: A device for digitally protecting against an overvoltage event may include a front-end circuit, an overvoltage protection circuit, and a protection switch. The protection switch may be coupled to the overvoltage protection circuit and may be configured to decouple the front-end circuit from an external medium, in response to a clamp signal. The overvoltage protection circuit may be configured to detect the overvoltage event at one or more nodes of a circuit. In response to the detection of the overvoltage event, the overvoltage protection circuit may generate the clamp signal to activate the protection switch.Type: ApplicationFiled: September 30, 2013Publication date: March 26, 2015Applicant: BROADCOM CORPORATIONInventors: Jan Roelof WESTRA, Jan MULDER, Qiongna ZHANG, Jeffrey Allan RILEY, Davide VECCHI
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Publication number: 20140177768Abstract: A receiver is disclosed that is capable of correcting for harmonic distortion injected into received analog signals. The receiver splits the analog signal in the analog front-end and modifies the split analog signals with a difference signal. After amplification and/or sampling, the modified analog signals are recombined in a main data pathway and are kept separate in a secondary pathway. Utilizing the difference signal, a feedback loop that includes distorters and an LMS filter detects the distortion coefficient of the harmonic distortion. A distorter in the main data pathway utilizes the detected distortion coefficient to correct the harmonic distortion in the analog signal.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: Broadcom CorporationInventors: Frank van der Goes, Jan Roelof Westra
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Patent number: 8447242Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.Type: GrantFiled: November 9, 2011Date of Patent: May 21, 2013Assignee: Broadcom CorporationInventors: Jan Roelof Westra, Rudy J. Van De Plassche, Chi-Hung Lin
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Publication number: 20120058736Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.Type: ApplicationFiled: November 9, 2011Publication date: March 8, 2012Applicant: Broadcom CorporationInventors: Jan Roelof Westra, Rudy J. van de Plassche, Chi-Hung Lin
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Patent number: 8081932Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.Type: GrantFiled: April 10, 2006Date of Patent: December 20, 2011Assignee: Broadcom CorporationInventors: Jan Roelof Westra, Rudy J. van de Plassche, Chi-Hung Lin
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Patent number: 7551035Abstract: A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.Type: GrantFiled: August 24, 2006Date of Patent: June 23, 2009Assignee: Broadcom CorporationInventors: Jan Roelof Westra, Franciscus Maria Leonardus van der Goes, Erol Arslan
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Patent number: 7324038Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: July 24, 2003Date of Patent: January 29, 2008Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Ruby van de Plassche, Marcel Lugthart
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Publication number: 20070182605Abstract: A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.Type: ApplicationFiled: August 24, 2006Publication date: August 9, 2007Applicant: Broadcom CorporationInventors: Jan Roelof Westra, Franciscus Maria Leonardus van der Goes, Erol Arslan
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Patent number: 7098829Abstract: A unit cell for a digital to analog conversion circuit that includes a current source (CS); a first data switch (S1) coupled to the current source (CS); a second data switch (S2) coupled to the current source (CS); a first phase switch (Phi1) coupled between the current source (CS) and the first data switch (S1); a second phase switch (Phi2) coupled between the current source (CS) and the second data switch (S2); a controller arranged to switch between the first (Phi1) and second (Phi2) phase switches in a Break Before Make alternating sequence, and to switch the first (S1) and second (S2) data switches in a Make Before Break sequence.Type: GrantFiled: March 19, 2003Date of Patent: August 29, 2006Assignee: Koninklijke Philips Electronics N.V.Inventor: Jan Roelof Westra
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Publication number: 20040155807Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output ofthe coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: ApplicationFiled: July 24, 2003Publication date: August 12, 2004Applicant: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Publication number: 20030218556Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: ApplicationFiled: February 6, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Patent number: 6653966Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: February 6, 2003Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Patent number: 6583747Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: May 31, 2002Date of Patent: June 24, 2003Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart