Abstract: A backplane for an electronic data communication system is disclosed. The backplane comprises at least one ultra-wideband transmitter configured to transmit data in the form of a plurality of pulses in a wireless manner and at least one ultra-wideband receiver configured to receive the plurality of pulses and decode the plurality of pulses to retrieve the data. The data is to be transmitted wirelessly from a first module comprising the at least one ultra-wideband transmitter to a second module comprising the ultra-wideband receiver within the electronic communication system, the first and second modules residing in the system housing.

Abstract: A synchronous serial bus features a variable data size format and an in-line addressing and data architecture. Flexible addressing allows for a variety of slave devices and configurations. Frequent parity checking during a transaction allows for faster error recovery. Repeater devices connect multiple slaves to the master using only point-to-point physical connections, thus providing multidrop architecture while at the same time ensuring excellent signal integrity and allowing a very high speed operation.

Abstract: A boot-up operation system is provided. In one exemplary embodiment, the system includes a CPU, a bootstrap memory, a boot memory, a main memory, an I/O port and CPU operating system code. When the system is turned on, the CPU executes the bootstrap program which directs it to determine whether the boot memory contains the necessary code to perform the boot-up operation. If the boot memory contents are usable for boot-up operation, the CPU starts executing a boot program that is stored in the boot memory. If the boot memory contents are not usable for boot-up operation, the bootstrap program directs the CPU to download a copy of the CPU operating system code from outside the system using the I/O port. After the download, the CPU stores a copy of the downloaded operating system code and the boot program into the boot memory for future use.

Abstract: A synchronous serial bus features a variable data size format and an in-line addressing and data architecture. Flexible addressing allows for a variety of slave devices and configurations. Frequent parity checking during a transaction allows for faster error recovery. Repeater devices connect multiple slaves to the master using only point-to-point physical connections, thus providing multidrop architecture while at the same time ensuring excellent signal integrity and allowing a very high speed operation.

Abstract: The presence and stability of the input digital video signal of a digital video device, such as a digital video tape recorder system, is determined by a system control microprocessor running a program for periodically reading signals from an input data clock presence detector circuit, a circuit detecting presence of timing reference code words in the input digital video signal, and circuits measuring rates of single-bit and multiple-bit errors in the detected timing reference code words. The input signal is determined present and stable if the input data clock is present, timing reference code words are present, and if measured sync data error rates do not exceed some experimentally determined threshold values.

Abstract: A method and apparatus for input data clock presence detection which utilizes an up/down counter clocked by a reference clock, which operates at a nominal frequency rate half of the nominal rate of the input data clock, and an R/S flip-flop causing the up/down counter to count up when set, and to count down when reset. The R/S flip-flop is cleared by the reference clock and set by the input data clock. The counter is selected to count up to its maximum number and remain there when continuously clocked up. Similarly, when continuously clocked down, the counter reaches its minimum number (zero) and remains there. So long as the input data clock is present and has the correct rate, after each reference clock pulse resets the flip-flop and prepares the counter to count down, there is at least one input data clock that sets the flip-flop and prepares the counter to count up.

Abstract: An apparatus and method are provided for controlling the level of an audio output signal which has been recorded and is played back from a magnetic tape at a low or zero tape speed, such as utilized in jog mode or variable speed playback during editing. A gain control signal is provided to eliminate a disturbing repetitive audio signal which accompanies stop motion playback and to reduce that signal level at low tape speed playback. The gain control signal is made dependent on the magnitude of tape speed, and it is applied to adjust the audio output gain of the playback channel.

Abstract: A time base corrector including a frame memory and a memory control. The memory control is microprocessor based and calculates the starting addresses of memory areas at which video data will be written to or read from the frame memory and the starting times of those sequences. The memory control receives information concerning the configuration of the time base corrector, the input video field sequence, the desired output video field sequence, timing components of the input and reference clock signals, TV standard, and operator commands to make these calculations. The results of the control are time base corrections for horizontal and vertical phase errors, horizontal and vertical positioning control, color frame sequencing, color correction of chroma phase, configuration delay adjustment, and other advantageous operations.

Abstract: A time base corrector is comprised of a plurality of system function modules implementing the functions for time base correcting an analog composite color video signal with a stable reference video signal. The system function modules obtain control data and communicate status data to a system control through a plurality of module function registers located in each module. The module function registers are connected to and selectable by a system bus of a microprocessor. The microprocessor has the module function registers mapped as addresses in its memory space to provide an architecture for communication and control of each function module by the system control.

Abstract: A system and method for controlling the phase of an output signal relative to the phase of a reference signal are described. A function generator receives a phase control input signal and generates a predetermined periodic waveform having a selected phase displacement with respect to the phase control input signal. A desired phase displacement of the generated waveform is provided in a digital manner by selecting and storing a set of digital values representing samples of the phase displaced waveform. The phase displaced waveform is generated from the set of stored digital sample values.

Abstract: A serial data communication system including a microprocessor and an asynchronous communication interface adapter (ACIA) implementing a SMPTE Supervisory Protocol for Digital Interface Control. The system detects the beginning of a break character as the first framing error which occurs after the last word of a data block has been detected. The receive clock of the ACIA is disabled in response to the start of break detection by the software reset of a bistable device which disables a receive clock gate. The framing error detection circuit of the ACIA is additionally disabled by the termination of the receive clock signal. The end of the break character is detected as the space to mark transition before the start of the first word in the data block. The receive clock is enabled by setting the bistable device with the end of break transition thereby detecting the termination of the break character and enabling the receive clock gate.

Abstract: A digital time base corrector for correcting time base errors of the digital samples of a video signal for all the various speed modes of a reproducing apparatus. The time base corrector is configured having a small capacity memory and a large capacity memory wherein the small capacity memory is divided into a first section and a second section. The first section of the small capacity memory retimes data samples for subcarrier phase errors without losing or repeating data, while the second section of the small capacity memory retimes data for horizontal frequency error without losing or repeating data in all reproducing modes except shuttle. Further, the second section of the small capacity memory in reverse and forward shuttle retimes the data for horizontal frequency and phase errors while equalizing the data rate through the time base corrector by selectively discarding or repeating horizontal lines based on line type.

Abstract: A time base corrector including a frame memory and a memory control. The memory control is microprocessor based and calculates the starting addresses of memory areas at which video data will be written to or read from the frame memory and the starting times of those sequences. The memory control receives information concerning the configuration of the time base corrector, the input video field sequence,the desired output video field sequence, timing components of the input and reference clock signals, TV standard, and operator commands to make these calculations. The results of the control are time base corrections for horizontal and vertical phase errors, horizontal and vertical positioning control, color frame sequencing, color correction of chroma phase, configuration delay adjustment, and other advantageous operations.

Abstract: An apparatus for controlling the phase of a video data signal to effect color correction includes a video data memory and memory control circuit. Interlaced write and read portions of the memory cycle are selectively spaced in time within a memory read/write cycle to enable shifting the read portion by a selected fraction of the memory read/write cycle without affecting the write portion, whereby color correction is achieved.