Patents by Inventor Jan Stephens
Jan Stephens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11992981Abstract: The invention refers to a method for producing expanded polymer pellets, which comprises the following steps: melting a polymer comprising a polyamide; adding at least one blowing agent; expanding the melt through at least one die for producing an expanded polymer; and pelletizing the expanded polymer. The invention further concerns polymer pellets produced with the method as well as their use, e.g. for the production of cushioning elements for sports apparel, such as for producing soles or parts of soles of sports shoes. A further aspect of the invention concerns a method for the manufacture of molded components, comprising loading pellets of an expanded to polymer material into a mold, and connecting the pellets by providing heat energy, wherein the expanded polymer material of the pellets or beads comprises a chain extender. The molded components may be used in broad ranges of application.Type: GrantFiled: August 11, 2021Date of Patent: May 28, 2024Assignee: adidas AGInventors: Christopher Edward Holmes, Tru Huu Minh Le, Sabrina Kerling, Dharan Kirupanantham, Volker Altstädt, Amir Fathi, Daniel Raps, Clemens Keilholz, Thomas Koeppl, Paul Smith, Jan Hill, Angus Wardlaw, Daniel Stephen Price, James Tarrier, Christopher Robertson
-
Patent number: 11973697Abstract: Embodiments of systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices are disclosed. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.Type: GrantFiled: January 10, 2022Date of Patent: April 30, 2024Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Patent number: 11966573Abstract: Technologies are disclosed for temporarily hiding user interface (“UI”) elements, such as application windows or tabs. A request can be received to hide a UI element for a specified period of time. When such a request is received, the UI element is hidden and an identifier corresponding to the UI element is moved from a first area of a taskbar to a second area of the taskbar. The application presenting the UI element can be configured for reduced consumption of computing resources while the UI element is hidden. Additionally, notifications associated with the UI element can be disabled while the UI element is hidden. When the specified period of time to hide the UI element has elapsed, the UI element is once again displayed. Additionally, the identifier corresponding to the UI element is moved from the second area of the taskbar back to the first area of the taskbar.Type: GrantFiled: June 2, 2021Date of Patent: April 23, 2024Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Jan-Kristian Markiewicz, Jerome Stephen Healy, Tiffany Jamie Chen
-
Patent number: 11960459Abstract: Systems and methods are described for merging customer profiles, such as may be implemented by a computer-implemented contact center service. In some aspects, a subset of profiles may be determined that satisfy merging criteria, where individual profiles include a plurality of data fields. At least one value in a first data field that conflicts between at least two profiles may be identified. Next a merged value may be selected for the first data field based on data deduplication criteria, where the data deduplication criteria includes at least one indicator of accuracy of values of the plurality of data fields. As a result of a determination that at least the subset of profiles of the group of profiles meet the merging criteria, at least the subset of profiles may be combined into a combined profile using the merged value.Type: GrantFiled: September 30, 2021Date of Patent: April 16, 2024Assignee: Amazon Technologies, Inc.Inventors: Jan Henrik Jonsson, Shadie Hijazi, Davor Golac, Kuangyou Yao, Yang Song, Shobhit Gupta, Ian James Boetius MacClancy, Lanxin Zhang, Hongtao Liu, Austin M Nevins, Amy Lee, Meng Xiao Wang, Blake Stephens
-
Patent number: 11677662Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.Type: GrantFiled: February 1, 2021Date of Patent: June 13, 2023Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20220417177Abstract: An embodiment of a segmented directional torus network on a chip (NOC) is disclosed. The provision of shortcut routers within directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth. A shortcut router may be efficiently technology mapped into fracturable FPGA lookup tables.Type: ApplicationFiled: January 10, 2022Publication date: December 29, 2022Applicant: Gray Research LLCInventor: Jan Stephen Gray
-
Patent number: 11455171Abstract: A fast and frugal item-state tracking scoreboard circuit is disclosed. The scoreboard maintains per-item partial states across multiple memory circuits, enabling multiple lookups per clock cycle and multiple state updates per clock cycle. In an embodiment a scoreboard is used to schedule instructions in an out-of-order processor. Each clock cycle the scoreboard indicates the busy state of an instruction's registers and may update the busy state of the destination registers of issuing instructions and completing instructions. Applications include register tracking, function-unit tracking, and cache-line state tracking, in embodiments including processor cores (including superscalar, superpipelined, and multithreaded processors), accelerators, memory systems, and networks. In an embodiment, a register-busy scoreboard circuit is implemented using FPGA LUT RAM memory.Type: GrantFiled: May 29, 2020Date of Patent: September 27, 2022Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Patent number: 11223573Abstract: An embodiment of a segmented directional torus network on a chip (NOC) is disclosed. The provision of shortcut routers within directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth. A shortcut router may be efficiently technology mapped into fracturable FPGA lookup tables.Type: GrantFiled: March 9, 2020Date of Patent: January 11, 2022Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20210160177Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Applicant: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20210117201Abstract: A fast and frugal item-state tracking scoreboard circuit is disclosed. The scoreboard maintains per-item partial states across multiple memory circuits, enabling multiple lookups per clock cycle and multiple state updates per clock cycle. In an embodiment a scoreboard is used to schedule instructions in an out-of-order processor. Each clock cycle the scoreboard indicates the busy state of an instruction's registers and may update the busy state of the destination registers of issuing instructions and completing instructions. Applications include register tracking, function-unit tracking, and cache-line state tracking, in embodiments including processor cores (including superscalar, superpipelined, and multithreaded processors), accelerators, memory systems, and networks. In an embodiment, a register-busy scoreboard circuit is implemented using FPGA LUT RAM memory.Type: ApplicationFiled: May 29, 2020Publication date: April 22, 2021Applicant: Gray Research LLCInventor: Jan Stephen Gray
-
Patent number: 10911352Abstract: A system and method for multicast delivery of messages using a configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router is well suited for implementation in programmable logic in FPGAs and achieves theoretical lower bounds on FPGA resource consumption. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The NOC may transmit a unicast message from one source client core to one destination client core, or a multicast message from one source client core to a plurality of destination client cores, or an arbitrary mix of unicast and multicast messages, simultaneously. A multicast message destination may include all client cores of routers with a particular first or second dimension coordinate, or all client cores, or some arbitrary subsets of client cores.Type: GrantFiled: September 16, 2019Date of Patent: February 2, 2021Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20200259743Abstract: A system and method for multicast delivery of messages using a configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router is well suited for implementation in programmable logic in FPGAs and achieves theoretical lower bounds on FPGA resource consumption. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The NOC may transmit a unicast message from one source client core to one destination client core, or a multicast message from one source client core to a plurality of destination client cores, or an arbitrary mix of unicast and multicast messages, simultaneously. A multicast message destination may include all client cores of routers with a particular first or second dimension coordinate, or all client cores, or some arbitrary subsets of client cores.Type: ApplicationFiled: September 16, 2019Publication date: August 13, 2020Applicant: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20200213245Abstract: An embodiment of a segmented directional torus network on a chip (NOC) is disclosed. The provision of shortcut routers within directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth. A shortcut router may be efficiently technology mapped into fracturable FPGA lookup tables.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Applicant: Gray Research LLCInventor: Jan Stephen Gray
-
Patent number: 10587534Abstract: Embodiments of systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices are disclosed. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.Type: GrantFiled: April 4, 2018Date of Patent: March 10, 2020Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Patent number: 10419338Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router is well suited for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router may employ an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics. A great diversity of NOC client cores, for communication amongst various external interfaces and devices, and on-chip interfaces and resources, may be coupled to a router in order to efficiently communicate with other NOC client cores.Type: GrantFiled: September 25, 2018Date of Patent: September 17, 2019Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20190028387Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router is well suited for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router may employ an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics. A great diversity of NOC client cores, for communication amongst various external interfaces and devices, and on-chip interfaces and resources, may be coupled to a router in order to efficiently communicate with other NOC client cores.Type: ApplicationFiled: September 25, 2018Publication date: January 24, 2019Applicant: Gray Research LLCInventor: Jan Stephen Gray
-
Patent number: 10116557Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics.Type: GrantFiled: December 31, 2015Date of Patent: October 30, 2018Assignee: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20180287964Abstract: Embodiments of systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices are disclosed. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.Type: ApplicationFiled: April 4, 2018Publication date: October 4, 2018Applicant: Gray Research LLCInventor: Jan Stephen Gray
-
Publication number: 20170220499Abstract: An embodiment of a massively parallel computing system comprising a plurality of processors, which may be subarranged into clusters of processors, and interconnected by means of a configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The system further comprises diverse high bandwidth external I/O devices and interfaces, which may include without limitation Ethernet interfaces, and dynamic RAM (DRAM) memories. The system is designed for implementation in programmable logic in FPGAs, but may also be implemented in other integrated circuit technologies, such as non-programmable circuitry, and in integrated circuits such as application-specific integrated circuits (ASICs). The system enables the practical implementation of diverse FPGA computing accelerators to speed up computation for example in data centers or telecom networking infrastructure. The system uses the NOC to interconnect processors, clusters, accelerators, and/or external interfaces.Type: ApplicationFiled: January 4, 2017Publication date: August 3, 2017Inventor: Jan Stephen Gray
-
Publication number: 20160344629Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics.Type: ApplicationFiled: December 31, 2015Publication date: November 24, 2016Inventor: Jan Stephen GRAY