Abstract: The present disclosure relates to a memory device comprising a memory array and a periphery circuitry configured to read data from and/or write data to the memory array, wherein the periphery circuitry comprises a programmable circuitry causing the memory device to access data stored in the memory array in accordance with manifest loop instructions. The programmable circuitry comprises a control logic configured to control the operation of the periphery circuitry in accordance with a set of parameters derived from the manifest loop instructions. The present disclosure further relates to a method for controlling the operation of a memory device and to a processing system comprising the memory device.

Abstract: The present disclosure discloses an apparatus and method for monitoring performance of an integrated circuit. The apparatus includes a delay line, which receives a pulse signal. The delay line has a controllable, variable length and propagates the pulse signal through a set length. The apparatus also includes a comparator, which receives the propagated pulse signal from the delay line and a clock signal, the comparator being arranged to determine whether the received signal is received early or late. The apparatus also includes a feedback loop, which receives input from the comparator for dynamically increasing or decreasing the set length of the delay line in dependence of the determination by the comparator. The apparatus determines a speed of the integrated circuit based on a determination by the comparator that the signal from the delay line closely matches the clock signal.