Patents by Inventor Jan Vincent C. Mancelita

Jan Vincent C. Mancelita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140070329
    Abstract: A wireless multichip module has a leadframe structure 10 with potions for receiving flip-chip mounted dies, including an integrated circuit 20 and high and low side mosfets 30, 40 to form a half-bridge circuit encapsulated in molding compound 70. The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor 150 or an internal input capacitor 350.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 13, 2014
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Allan Tungul Flores, Romel N. Manatad, Jan Vincent C. Mancelita
  • Publication number: 20120168947
    Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
    Type: Application
    Filed: February 24, 2012
    Publication date: July 5, 2012
    Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita
  • Patent number: 8158506
    Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: April 17, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita