Patents by Inventor Jan-Wen You
Jan-Wen You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7643976Abstract: Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.Type: GrantFiled: June 1, 2006Date of Patent: January 5, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Jung Shin, King-Chang Shu, Jan-Wen You, Tsai-Sheng Gau
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Patent number: 7474788Abstract: An image processing system. An input/output device receives information for pixels in an image corresponding to an object, wherein the information specifies optical properties. A storage device stores the information. A processor determines an image of preliminary contour of the object based on the information. For pixels located on the preliminary contour are assigned as primary pixels, wherein anchor points determined by the location of the primary pixels, and the reference pixels determine modification vectors according to the information corresponding to the primary and reference pixels, and adjusts the positions of the anchor points according to the modification vectors. These processes are applied on every pixels or selected pixels located on the preliminary contour repeatedly to determine the final modified contour with sub-pixel accuracy.Type: GrantFiled: September 8, 2004Date of Patent: January 6, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Ming Chang, Wen-Chuan Wang, Jan-Wen You
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Publication number: 20070203680Abstract: Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.Type: ApplicationFiled: June 1, 2006Publication date: August 30, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Jung Shin, King-Chang Shu, Jan-Wen You, Tsai-Sheng Gau
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Patent number: 7234128Abstract: A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.Type: GrantFiled: October 3, 2003Date of Patent: June 19, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Sheng Gau, Jaw-Jung Shin, Jan-Wen You, Burn-Jeng Lin
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Publication number: 20070087291Abstract: A method and associated masks for carrying out a lithographic imaging process to reduce or avoid a strong interference effect in off-axis illumination, the method including providing a resist layer on a substrate; illuminating a first group of line patterns through a first mask on the resist layer; illuminating a second group of line patterns through a second mask on the resist layer, the second group of line patterns oriented nonparallel with respect to the first group of line patterns; and, developing the illuminated resist layer.Type: ApplicationFiled: October 18, 2005Publication date: April 19, 2007Inventors: Tsai-Sheng Gau, Jaw-Jung Shin, Chun-Kuang Chen, Jan-Wen You, Burn-Jeng Lin
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Patent number: 7175941Abstract: Prior art methods for forming alt. PSMs require a relatively large number of phase assignments to avoid phase conflicts in complex arrays. This has been improved by adding dummy elements at the ends of all rows and columns of the array that is to be imaged, while initially leaving all corners open. Phases are then assigned in checker board fashion to all elements. Additional dummy elements are then placed in the open corners and assigned the same phase as their immediate neighbors. The first exposure of the photoresist is made with both the original elements and the additional dummy elements. Then additional resist is coated and exposed and the original elements are open after development. If the added elements are made somewhat smaller than the original elements, only a single exposure is used.Type: GrantFiled: September 8, 2003Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaw-Jung Shin, Jan-Wen You
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Patent number: 7131102Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.Type: GrantFiled: February 19, 2004Date of Patent: October 31, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin
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Patent number: 7036108Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.Type: GrantFiled: February 18, 2004Date of Patent: April 25, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin
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Patent number: 7013453Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.Type: GrantFiled: February 18, 2004Date of Patent: March 14, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin
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Publication number: 20060050965Abstract: An image processing system. An input/output device receives information for pixels in an image corresponding to an object, wherein the information specifies optical properties. A storage device stores the information. A processor determines an image of preliminary contour of the object based on the information. For pixels located on the preliminary contour are assigned as primary pixels, wherein anchor points determined by the location of the primary pixels, and the reference pixels determine modification vectors according to the information corresponding to the primary and reference pixels, and adjusts the positions of the anchor points according to the modification vectors. These processes are applied on every pixels or selected pixels located on the preliminary contour repeatedly to determine the final modified contour with sub-pixel accuracy.Type: ApplicationFiled: September 8, 2004Publication date: March 9, 2006Inventors: Shih-Ming Chang, Wen-Chuan Wang, Jan-Wen You
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Patent number: 6973636Abstract: A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.Type: GrantFiled: October 17, 2003Date of Patent: December 6, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Burn-Jeng Lin, Li-Chun Tien, Mi-Chang Chang, Yu-Jun Chou, Jan-Wen You, King-Chang Shu, Li-Jui Chen
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Publication number: 20050086629Abstract: A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Inventors: Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Burn-Jeng Lin, Li-Chun Tien, Mi-Chang Chang, Yu-Jun Chou, Jan-Wen You, King-Chang Shu, Li-Jui Chen
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Publication number: 20050076323Abstract: A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.Type: ApplicationFiled: October 3, 2003Publication date: April 7, 2005Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsai-Sheng Gau, Jaw-Jung Shin, Jan-Wen You, Burn-Jeng Lin
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Publication number: 20050053846Abstract: Prior art methods for forming alt. PSMs require a relatively large number of phase assignments to avoid phase conflicts in complex arrays. This has been improved by adding dummy elements at the ends of all rows and columns of the array that is to be imaged, while initially leaving all corners open. Phases are then assigned in checker board fashion to all elements. Additional dummy elements are then placed in the open corners and assigned the same phase as their immediate neighbors. The first exposure of the photoresist is made with both the original elements and the additional dummy elements. Then additional resist is coated and exposed and the original elements are open after development. If the added elements are made somewhat smaller than the original elements, only a single exposure is used.Type: ApplicationFiled: September 8, 2003Publication date: March 10, 2005Inventors: Jaw-Jung Shin, Jan-Wen You
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Publication number: 20040168146Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.Type: ApplicationFiled: February 18, 2004Publication date: August 26, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin
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Publication number: 20040168147Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.Type: ApplicationFiled: February 18, 2004Publication date: August 26, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin
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Publication number: 20040161679Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.Type: ApplicationFiled: February 19, 2004Publication date: August 19, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin
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Patent number: 6711732Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.Type: GrantFiled: July 26, 2002Date of Patent: March 23, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin