Abstract: A clock recovery system includes a rough clock generator, which yields a rough clock signal, based upon logic level transitions exhibited by a data signal. The rough clock signal is supplied to a phase locked loop having an adjustable order of frequency response, an adjustable corner frequency, an adjustable natural frequency, and/or an adjustable damping factor. The clock recovery system includes control parameters that, when properly adjusted, suppress non-ideal effects of components within the clock recovery system, and also permit the frequency response of the phase locked loop to be returned to a desired response.

Abstract: A method and system for removing the effect of intersymbol interference (ISI) from a data record indicating times of logic level transitions exhibited by a data signal that has been distorted by ISI exhibited by a system having a particular step response may perform the following acts. The data record may be received, and a transition from within the data may be selected record for removal of ISI. Preceding transitions within the data record are then inspected. A time defect is obtained, based at least in part upon the inspected preceding transitions. Finally, the data record is adjusted, based upon the time defect, to indicate a new time of transition for the selected transition, thereby removing the effect of ISI for the selected transition.

Abstract: A method, apparatus, and article of manufacture for analyzing measurements. The invention provides a method for separating and analyzing the components of a distribution, such as deterministic and random components. The method performs the steps of collecting data from a measurement apparatus, constructing a histogram based on the data such that the histogram defines a distribution, fitting tails regions wherein deterministic and random components and associated statistical confidence levels are estimated.

Abstract: An event counter circuit including an input signal coupled to a frequency divider circuit that can be cleared by an external signal, a multiplexer coupled to the divider circuit driven by an output edge and its inverse, and a counter circuit coupled to the multiplexer driven by outputs of the multiplexer.