Patents by Inventor Jan Wouter BIJLSMA

Jan Wouter BIJLSMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11875101
    Abstract: A patterning process modeling method includes determining, with a front end of a process model, a function associated with process physics and/or chemistry of an operation within a patterning process flow; and determining, with a back end of the process model, a predicted wafer geometry. The back end includes a volumetric representation of a target area on the wafer. The predicted wafer geometry is determined by applying the function from the front end to manipulate the volumetric representation of the wafer. The volumetric representation of the wafer may be generated using volumetric dynamic B-trees. The volumetric representation of the wafer may be manipulated using a level set method. The function associated with the process physics and/or chemistry of the operation within the patterning process flow may be a velocity/speed function. Incoming flux on a modeled surface of the wafer may be determined using ray tracing.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: January 16, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Jen-Shiang Wang, Feng Chen, Matteo Alessandro Francavilla, Jan Wouter Bijlsma
  • Publication number: 20220260921
    Abstract: A patterning process modeling method includes determining, with a front end of a process model, a function associated with process physics and/or chemistry of an operation within a patterning process flow; and determining, with a back end of the process model, a predicted wafer geometry. The back end includes a volumetric representation of a target area on the wafer. The predicted wafer geometry is determined by applying the function from the front end to manipulate the volumetric representation of the wafer. The volumetric representation of the wafer may be generated using volumetric dynamic B-trees. The volumetric representation of the wafer may be manipulated using a level set method. The function associated with the process physics and/or chemistry of the operation within the patterning process flow may be a velocity/speed function. Incoming flux on a modeled surface of the wafer may be determined using ray tracing.
    Type: Application
    Filed: May 25, 2020
    Publication date: August 18, 2022
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jen-Shiang WANG, Feng CHEN, Matteo Alessandro FRANCAVILLA, Jan Wouter BIJLSMA
  • Patent number: 10296681
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 21, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Guangqing Chen, Shufeng Bai, Eric Richard Kent, Yen-Wen Lu, Paul Anthony Tuffy, Jen-Shiang Wang, Youping Zhang, Gertjan Zwartjes, Jan Wouter Bijlsma
  • Publication number: 20180268093
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: ASML Netherlands B.V.
    Inventors: Guangqing CHEN, Shufeng Bai, Eric Richard Kent, Yen-Wen Lu, Paul Anthony Tuffy, Jen-Shiang Wang, Youping Zhang, Gertjan Zwartjes, Jan Wouter Bijlsma
  • Patent number: 10007744
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 26, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Guangqing Chen, Shufeng Bai, Eric Richard Kent, Yen-Wen Lu, Paul Anthony Tuffy, Jen-Shiang Wang, Youping Zhang, Gertjan Zwartjes, Jan Wouter Bijlsma
  • Publication number: 20160140267
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 19, 2016
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Guangqing CHEN, Shufeng BAI, Eric Richard KENT, Yen-Wen LU, Paul Anthony TUFFY, Jen-Shiang WANG, Youping ZHANG, Gertjan ZWARTJES, Jan Wouter BIJLSMA