Patents by Inventor Janak Patel

Janak Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118618
    Abstract: An electronic device includes (i) an integrated circuit (IC) die mounted on a substrate, (ii) a lid having first and second surfaces facing one another, and one or more openings formed through the lid between the first and second surfaces, the lid being disposed over at least the IC die to form a space between the IC die and the first surface of the lid, the one or more openings are configured to enable transference of fluids through the lid, (iii) a liquid thermal interface material (TIM) filling the space and being formulated to conduct heat from the IC die to the lid, and (iv) a stopper structure extended from the first surface of the lid, the stopper structure includes one or more sidewalls configured to contain the liquid TIM at least in the space between the IC die and the first surface of the lid.
    Type: Application
    Filed: October 1, 2024
    Publication date: April 10, 2025
    Inventors: Janak Patel, Assaad El Helou
  • Patent number: 11810832
    Abstract: A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: November 7, 2023
    Assignee: Marvell Asia Pte Ltd
    Inventors: Janak Patel, Richard Graf, Manish Nayini, Nazmul Habib
  • Publication number: 20230233396
    Abstract: An apparatus and method for use of an improved stretching device providing various stretches and manipulation of a user's muscle groups, including lower body muscle groups. Movement of the upper and lower support members can be achieved with a controller or wireless controller, such as a cellular phone executing an application operatively connected via a transceiver of the stretching device. The upper support member and lower support member may be independently controlled by a secondary motor assembly at a rotational connection between the support members. Some embodiments may provide removable support members for switching between left and right-side manipulation of a user's left and right legs with a single device. Other embodiments may include a track to allow for a sliding movement of the motor assembly or the upper and lower support members between left and right sides of the stretching device.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 27, 2023
    Inventor: Janak Patel
  • Publication number: 20230197635
    Abstract: A semiconductor package includes a package substrate, a semiconductor chip disposed on the package substrate, and a stiffener disposed on the package substrate. The stiffener includes an inner portion configured to surround the semiconductor chip, the inner portion defining a space on the package substrate external to the inner portion and located between the inner portion and outer edges of the package substrate, and a plurality of leg portions extending outwardly from the inner portion toward one or more of the outer edges of the package substrate and corners of the package substrate.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 22, 2023
    Inventors: Janak PATEL, Richard S. GRAF, Manish NAYINI
  • Publication number: 20210407879
    Abstract: A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 30, 2021
    Inventors: Janak PATEL, Richard GRAF, Manish NAYINI, Nazmul HABIB
  • Publication number: 20190378829
    Abstract: A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Janak PATEL, Subramanian Srikanteswara IYER, Daniel BERGER
  • Patent number: 10461067
    Abstract: A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Janak Patel, Subramanian Srikanteswara Iyer, Daniel Berger
  • Publication number: 20180068993
    Abstract: A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Inventors: Janak PATEL, Subramanian Srikanteswara IYER, Daniel BERGER
  • Publication number: 20180012878
    Abstract: A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Inventors: Janak PATEL, Subramanian Srikanteswara IYER, Daniel BERGER
  • Patent number: 9859262
    Abstract: A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Janak Patel, Subramanian Srikanteswara Iyer, Daniel Berger
  • Patent number: 5377197
    Abstract: A sequential circuit test generation system and method to generate test patterns for sequential without assuming the use of scan techniques or a reset state utilizes the iterative logic array (ILA) model of the sequential circuit and a targeted-D propagation scheme employing both forward time processing (FTP) and reverse time processing (RTP) techniques for assigning a sequence of primary input (PI) values and for producing a an initial pseudo primary input (PPI) vector representing the initial state of the digital circuit at a particular time frame. Improved state justification techniques generate the remaining sequence of PI vectors necessary to put the circuit into the initial state from either known or don't care first states, by means of a heuristic method for reducing required initial state assignments. The method can also be applied to reduce the required number of PI vector assignments is also presented.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: December 27, 1994
    Assignee: University of Illinois
    Inventors: Janak Patel, Thomas Niermann