Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.

Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.

Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

Abstract: A DLL circuit is disclosed. The DLL circuit includes a delay line, configured to receive a delay line input clock, and to generate a plurality of output clocks each having a phase based on a delay of the delay line. The DLL circuit also includes a control circuit, configured to selectively cause the delay line input clock to be equal to one of a DLL input clock and an inverted one of the output clocks of the delay line, and an edge combiner, configured to generate a DLL output clock based on the output clocks of the delay line.

Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a crystal oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some implementations, an adjustment block may be employed to adjust the count determined by the learning block based on one or more characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

Abstract: Apparatus and methods for performing wireless communications are provided. In some embodiments, an apparatus includes a transformer including a first winding, a second winding, and a third winding. The apparatus also includes a first transmitter circuit coupled with the first winding, and a second circuit coupled with the second winding. The third winding is coupled with an antenna. The first transmitter circuit is configured to transmit a first signal to the antenna via magnetic coupling between the first winding and the third winding. The second circuit is configured to tolerate without damage a second signal from the first transmitter circuit, wherein the second signal is generated from the first signal via magnetic coupling between the first winding and the second winding. A turn ratio between the first winding and the second winding can be configured to limit a voltage of the second signal to be within a pre-determined threshold.

Abstract: Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.

Abstract: Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.

Abstract: A switching-mode power amplifier includes a driver circuit having an input for receiving a radio frequency (RF) signal, an output for outputting a digital output signal, and a bias port for receiving a bias signal, and a bias circuit having a first input coupled to the output of the driver circuit for receiving the digital output signal, a second input coupled to the input of the driver circuit for receiving the RF signal, and an output coupled to the bias port of the driver circuit for providing the bias signal to the driver circuit.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a crystal oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some implementations, an adjustment block may be employed to adjust the count determined by the learning block based on one or more characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

Abstract: Apparatus and methods for performing wireless communications are provided. In some embodiments, an apparatus includes a transformer including a first winding, a second winding, and a third winding. The apparatus also includes a first transmitter circuit coupled with the first winding, and a second circuit coupled with the second winding. The third winding is coupled with an antenna. The first transmitter circuit is configured to transmit a first signal to the antenna via magnetic coupling between the first winding and the third winding. The second circuit is configured to tolerate without damage a second signal from the first transmitter circuit, wherein the second signal is generated from the first signal via magnetic coupling between the first winding and the second winding. A turn ratio between the first winding and the second winding can be configured to limit a voltage of the second signal to be within a pre-determined threshold.

Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some embodiments, an adjustment block may be employed to adjust the count determined by the learning block based on one or more measured characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

Abstract: A switching-mode power amplifier includes a driver circuit having an input for receiving a radio frequency (RF) signal, an output for outputting a digital output signal, and a bias port for receiving a bias signal, and a bias circuit having a first input coupled to the output of the driver circuit for receiving the digital output signal, a second input coupled to the input of the driver circuit for receiving the RF signal, and an output coupled to the bias port of the driver circuit for providing the bias signal to the driver circuit.

Abstract: Apparatus and methods for performing wireless communications are provided. In some embodiments, an apparatus includes a transformer including a first winding, a second winding, and a third winding. The apparatus also includes a first transmitter circuit coupled with the first winding, and a second circuit coupled with the second winding. The third winding is coupled with an antenna. The first transmitter circuit is configured to transmit a first signal to the antenna via magnetic coupling between the first winding and the third winding. The second circuit is configured to tolerate without damage a second signal from the first transmitter circuit, wherein the second signal is generated from the first signal via magnetic coupling between the first winding and the second winding. A turn ratio between the first winding and the second winding can be configured to limit a voltage of the second signal to be within a pre-determined threshold.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some embodiments, an adjustment block may be employed to adjust the count determined by the learning block based on one or more measured characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.