Patents by Inventor Janaki Sivaramakrishnan

Janaki Sivaramakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for improving efficacy of model verification by model partitioning
    Patent number: 11144684
    Abstract: A device may analyze, by one or more processors, a model to identify a first set of model elements that are associated with a model element. The device may apply, by the one or more processors, one or more results from an analysis of the model to a first network unit to determine a complexity of the first network unit or a coupling of the first network unit to other model elements of the model. The device may generate, by the one or more processors, a second network unit, representing a second hierarchy of computation, from the first network unit based on the complexity or the coupling. The device may provide, by the one or more processors, the second network unit as a testing unit for testing the model, the second network unit comprising two or more model elements and one or more numeric expressions.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 12, 2021
    Assignee: The MathWorks, Inc.
    Inventors: Dixit Manoj Gangadhar, Prahladavaradan Sampath, Janaki Sivaramakrishnan, William J. Aldrich, Ebrahim Mehran Mestchian
  • METHOD AND SYSTEM FOR IMPROVING EFFICACY OF MODEL VERIFICATION BY MODEL PARTITIONING
    Publication number: 20170351791
    Abstract: A device may analyze, by one or more processors, a model to identify a first set of model elements that are associated with a model element. The device may apply, by the one or more processors, one or more results from an analysis of the model to a first network unit to determine a complexity of the first network unit or a coupling of the first network unit to other model elements of the model. The device may generate, by the one or more processors, a second network unit, representing a second hierarchy of computation, from the first network unit based on the complexity or the coupling. The device may provide, by the one or more processors, the second network unit as a testing unit for testing the model, the second network unit comprising two or more model elements and one or more numeric expressions.
    Type: Application
    Filed: April 27, 2017
    Publication date: December 7, 2017
    Inventors: Dixit MANOJ GANGADHAR, Prahladavaradan Sampath, Janaki Sivaramakrishnan, William J. Aldrich, Ebrahim Mehran Mestchian