Patents by Inventor Janardhanan Pathangi Narasimhan

Janardhanan Pathangi Narasimhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9628375
    Abstract: Aspects of the present invention include an arbitrary N-Node virtual link trunking (VLT) system comprising a set of N nodes collectively provide a logical fabric-level view that is consistent across the set of N nodes. Embodiments of the arbitrary N-Node VLT system comprise a control plane mechanism to provide Layer 2 multipathing between access network devices (switches or servers) and the core network. The N-Node VLT system provides a loop-free topology with active-active load-sharing of uplinks from access to the core. Accordingly, the N-Node VLT system eliminates the disadvantage of Spanning Tree Protocol (STP) (active-standby links) by allowing link aggregation group (LAG) terminations on multiple separate distribution or core switches and also supporting a loop-free topology. Additional benefits of an N-Node VLT system include, but are not limited to, higher resiliency, improved link utilization, and improved manageability of the network.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: April 18, 2017
    Assignee: DELL PRODUCTS LP
    Inventors: Janardhanan Pathangi Narasimhan, Shivakumar Sundaram, Avinash Natarajan
  • Patent number: 9614727
    Abstract: Aspects of the present invention include an n-node link aggregation group (LAG) system comprising a set of N nodes collectively provide a logical fabric-level view that is consistent across the set of N nodes. Embodiments of the n-node system comprise a control plane mechanism to provide Layer 2 multipathing between access network devices and the core network. The n-node system provides a loop-free topology with active-active load-sharing of uplinks from access to the core.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: April 4, 2017
    Assignee: DELL PRODUCTS L.P.
    Inventors: Mohnish Anumala, Anoop Ghanwani, Krishnamurthy Subramanian, Janardhanan Pathangi Narasimhan, Shivakumar Sundaram
  • Publication number: 20160234100
    Abstract: Aspects of the present invention include an arbitrary N-Node virtual link trunking (VLT) system comprising a set of N nodes collectively provide a logical fabric-level view that is consistent across the set of N nodes. Embodiments of the arbitrary N-Node VLT system comprise a control plane mechanism to provide Layer 2 multipathing between access network devices (switches or servers) and the core network. The N-Node VLT system provides a loop-free topology with active-active load-sharing of uplinks from access to the core. Accordingly, the N-Node VLT system eliminates the disadvantage of Spanning Tree Protocol (STP) (active-standby links) by allowing link aggregation group (LAG) terminations on multiple separate distribution or core switches and also supporting a loop-free topology. Additional benefits of an N-Node VLT system include, but are not limited to, higher resiliency, improved link utilization, and improved manageability of the network.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Applicant: DELL PRODUCTS L.P.
    Inventors: Janardhanan Pathangi Narasimhan, Shivakumar Sundaram, Avinash Natarajan
  • Patent number: 9363167
    Abstract: A network switch suitable for receiving packets of information from and the packets of information to a communications network includes a plurality of physical ports, packet processing functionality and memory. The packet processing functionality operates on information stored in memory to determine the LAG, from among two or more LAGs, over which a packet received by the switch should be correctly forwarded. The switch memory stores a plurality of LAG tables, each one of which can include one or more entries comprising a physical port number and a packet parameter that are used by the packet processing functionality to determinately identify the correct LAG over which to forward a packet.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: June 7, 2016
    Assignee: Dell Products L.P.
    Inventor: Janardhanan Pathangi Narasimhan
  • Publication number: 20160149759
    Abstract: Aspects of the present invention include an n-node link aggregation group (LAG) system comprising a set of N nodes collectively provide a logical fabric-level view that is consistent across the set of N nodes. Embodiments of the n-node system comprise a control plane mechanism to provide Layer 2 multipathing between access network devices and the core network. The n-node system provides a loop-free topology with active-active load-sharing of uplinks from access to the core.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Applicant: DELL PRODUCTS L.P.
    Inventors: Mohnish Anumala, Anoop Ghanwani, Krishnamurthy Subramanian, Janardhanan Pathangi Narasimhan, Shivakumar Sundaram
  • Publication number: 20150003459
    Abstract: A network switch suitable for receiving packets of information from and the packets of information to a communications network includes a plurality of physical ports, packet processing functionality and memory. The packet processing functionality operates on information stored in memory to determine the LAG, from among two or more LAGs, over which a packet received by the switch should be correctly forwarded. The switch memory stores a plurality of LAG tables, each one of which can include one or more entries comprising a physical port number and a packet parameter that are used by the packet processing functionality to determinately identify the correct LAG over which to forward a packet.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 1, 2015
    Inventor: Janardhanan Pathangi Narasimhan