Patents by Inventor Janardhanan S. Aiit

Janardhanan S. Aiit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-voltage transistor with multi-layer conduction region
    Publication number: 20040217419
    Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.
    Type: Application
    Filed: June 3, 2004
    Publication date: November 4, 2004
    Applicant: Power Integrations, Inc.
    Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Aiit