Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same, the semiconductor device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate, including a plurality of first active fragments and a plurality of second active fragments. The first active fragments and the second active fragments are parallel and separately extended along a first direction, and the second active fragments are disposed outside all of the first active fragments. The first active fragments have a same length in the first direction, being a first length, the second active fragment have a second length in the first direction, and the second length is greater than the first length.

Abstract: A dynamic random access memory device includes a substrate having a first active region, a first isolation region, a second active region, and a second isolation region arranged in order along a first direction. A first bit line is disposed on the first active region and in direct contact with the first active region. A second bit line is disposed on the second isolation region. An insulating layer is disposed between and separate the second bit line and the second isolation region. A storage node contact structure is disposed between the first bit line and the second bit line and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.

Abstract: A memory device and a manufacturing thereof are disclosed in the present invention. The memory device includes a substrate, a bit line contact opening, a bit line contact structure, and a first spacer. The bit line contact opening is at least partially disposed in the substrate, and the bit line contact opening includes a first portion, a second portion, and a third portion. The second portion located under and connected with the first portion. The third portion is located under t and connected with the second portion. The bit line contact structure is disposed in the first portion, the second portion, and the third portion of the bit line contact opening. The first spacer is disposed in the first portion of the bit line contact opening and surrounds the bit line contact structure.

Abstract: A semiconductor device and a fabricating method thereof includes a substrate, a plurality of active areas, a plurality of shallow trench isolations, and a plurality of word lines. The active areas are disposed in the substrate. The shallow trench isolations are disposed in the substrate, wherein each of the shallow trench isolations includes a first insulating layer and a second insulating layer stacked in sequence, the first insulating layer physically contacts one of the active areas. The word lines are separately disposed in the substrate to respectively overlap the active areas and the shallow trench isolations, wherein the word lines comprise at least one first word line, at least a portion of the second insulating layer is disposed between a sidewall of the at least one first word line and the first insulating layer of a corresponding one of the shallow trench isolations.

Abstract: A semiconductor device includes a substrate, a plurality of active regions disposed in the substrate and respectively extending along a first direction and arranged into an array, and a plurality of isolation structures disposed in the substrate between the active regions. The isolation structures respectively comprise an upper portion and a lower portion, wherein a sidewall of the upper portion comprises a first slope, a sidewall of the lower portion comprises a second slop, and the first slope and the second slope are different. The semiconductor device further includes a plurality of semiconductor layers disposed between the upper portions of the isolation structures and the active regions.

Abstract: A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

Abstract: The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Abstract: A semiconductor structure includes a substrate, a first bottom electrode and a second bottom electrode disposed on the substrate, an upper supporting layer extending laterally between the first bottom electrode and the second bottom electrode and directly contacting the first bottom electrode and the second bottom electrode, a cavity between the upper sacrificial layer and the substrate, a capacitor dielectric layer covering along the first bottom electrode and the second bottom electrode, and a conductive material disposed on the capacitor dielectric layer. A portion of the first bottom electrode has a slope profile having a lower end not lower than a lower surface of the upper supporting layer.

Abstract: In a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, conductive layer structures, plug structures, spacers and stop layers. The plug structures are disposed between two of the conductive layer structures in a second direction perpendicular to the first direction. The spacers are disposed between the conductive layer structures and the plug structures. The stop layers are disposed on the spacers between the conductive layer structures and the plug structures and has a bottommost surface disposed between a bottom surface of the conductive layer structures and a bottom surface of the spacers. The plug structures comprise at least one protrusion member extending from the bottommost surface toward the conductive layer structure and disposed between the stop layer and the substrate. Accordingly, contact area between the plug structures and the substrate can be increased.

Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.

Abstract: A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.

Abstract: A semiconductor device includes a substrate, a connecting layer on the substrate, and a capacitor structure arranged on the connecting layer. The connecting layer includes an array of connecting pads, a peripheral structure adjacent to the array of connecting pads, and a plurality of first extending pads arranged between the peripheral structure and the array of connecting pads. The connecting pads respectively have one of the bottom electrodes of the capacitor structure disposed thereon. The first extending pads respectively have two of the bottom electrodes of the capacitor structure disposed thereon to reinforce the peripheral portions of the capacitor structure.

Abstract: A contact pad structure and a manufacturing method thereof are disclosed in the present invention. The contact pad structure includes a substrate, a first dielectric layer, a second dielectric layer, first contact pads, an etching stop layer, a first void, and a second void. The first contact pads are disposed on a first region of the substrate. The first dielectric layer is disposed on the substrate, covers the first contact pads, and includes a recess located between two adjacent first contact pads. The etching stop layer is disposed on the first dielectric layer and partially located in the recess. The second dielectric layer is disposed on the etching stop layer and partially located in the recess. The first void is disposed in the etching stop layer and located in the recess. The second void is disposed in the second dielectric layer and located in the recess.

Abstract: A method for forming a semiconductor structure includes providing a substrate, forming an upper sacrificial layer, an upper supporting layer and a hard mask layer on the substrate, forming bottom electrodes through the upper sacrificial layer, the upper supporting layer and the hard mask layer, forming at least an opening between the bottom electrodes and through the hard mask layer and the upper supporting layer to partially expose the upper sacrificial layer. A portion of at least one of the bottom electrodes exposed from the opening has a slope profile, and a lower end of the slope profile is not lower than a lower surface of the upper supporting layer. The method further includes removing the upper sacrificial layer from the opening to form a cavity, and forming a capacitor dielectric layer along the bottom electrodes and a conductive material filling the cavity.

Abstract: The present disclosure provides a semiconductor memory device and a method of fabricating the same, including a substrate, a plurality of bit lines, a bit line contact, a spacer, a liner layer, and a storage node contact. The bit lines are separately disposed on the substrate. The bit line contact is disposed below one of the bit lines to extend into one active area. The spacer is disposed on sidewalls of each of the bit lines and the bit line contact. The liner layer is disposed on the substrate along an outer periphery of the bit line contact, wherein the liner layer comprises a first portion embedded in the one of the bit line, between the bit line contact and the one of the bit lines in an extending direction of the bit lines. The storage node contact and the bit lines are alternately arranged with each other.

Abstract: The present disclosure relates to a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of bit lines, and a plurality isolation fins. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are disposed in the substrate. The bit lines are disposed on the substrate. The isolation fins are disposed on the substrate, over each of the buried word lines respectively, wherein a portion of the isolation fins is disposed under the bit lines and overlapped with the bit lines.

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

Abstract: A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a semiconductor substrate, bit line structures, isolation structures, a storage node contact structure, and first voids. The bit line structures, the isolation structures, and the storage node contact structure are disposed on the semiconductor substrate. Each bit line structure extends in a first direction, and the bit line structures are arranged in a second direction. The isolation structures are located between the bit line structures adjacent to one another. The storage node contact structure is located between two adjacent bit line structures and located between two adjacent isolation structures in the first direction. The storage node contact structure includes four corner portions. The first voids are disposed in the storage node contact structure, and the first voids are located in at least two of the four corner portions.

Abstract: A semiconductor structure includes a substrate having a peripheral region and a memory region. A plurality of bit lines are disposed on the substrate, extending along a first direction to pass through the peripheral region and the memory region, and arranged in parallel along a second direction, wherein the first direction and the second direction are is perpendicular. A plurality of insulating plugs and first spacer structures are alternately arranged along the first direction between the bit lines on the peripheral region. A plurality of conductive plugs and second spacer structures are alternately arranged along the first direction between the bit lines on the memory region. The first spacer structures and the second spacer structures comprise a same material, and along the first direction, widths of the second spacer structures are smaller than widths of the first spacer structures.

Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same, which includes a substrate, a plurality of bit lines, a plurality of first plugs, a first spacer, a second spacer, a plurality of second plugs and a metal silicide layer. The bit lines are disposed on the substrate. The first plugs are disposed on the substrate and separated from the bit lines. The first spacer and the second spacer are disposed between each of the bit lines and the first plugs, and include a first height and a second height respectively. The second plugs are disposed on the first plugs respectively, and the metal silicide layer is disposed between the first plugs and the second plugs, wherein an end portion of the metal silicide layer is clamped between the second spacer and the first spacer.