Patents by Inventor Janes A. Yater
Janes A. Yater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7902022Abstract: A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.Type: GrantFiled: July 29, 2008Date of Patent: March 8, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Sung-Taeg Kang, Jane A. Yater
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Patent number: 7811886Abstract: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).Type: GrantFiled: February 6, 2007Date of Patent: October 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Taras A. Kirichenko, Konstantin V. Loiko, Ramachandran Muralidhar, Rajesh A. Rao, Sung-Taeg Kang, Ko-Min Chang, Jane Yater
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Publication number: 20100029052Abstract: A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventors: Sung-Taeg Kang, Jane A. Yater
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Patent number: 7642163Abstract: An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.Type: GrantFiled: March 30, 2007Date of Patent: January 5, 2010Assignee: Freescale Semiconductor, IncInventors: Rajesh A. Rao, Tushar P. Merchant, Ramachandran Muralidhar, Gowrishankar Chindalore, David Sing, Jane Yater
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Patent number: 7471560Abstract: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.Type: GrantFiled: August 6, 2007Date of Patent: December 30, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Jane A. Yater, Gowrishankar L. Chindalore, Cheong M. Hong
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Publication number: 20080242022Abstract: An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Rajesh A. Rao, Tushar P. Merchant, Ramachandran Muralidhar, Gowrishankar Chindalore, David Sing, Jane Yater
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Publication number: 20080188052Abstract: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).Type: ApplicationFiled: February 6, 2007Publication date: August 7, 2008Inventors: Brian A. Winstead, Taras A. Kirichenko, Konstantin V. Loiko, Ramachandran Muralidhar, Rajesh A. Rao, Sung-Taeg Kang, Ko-Min Chang, Jane Yater
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Publication number: 20080019178Abstract: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.Type: ApplicationFiled: August 6, 2007Publication date: January 24, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jane Yater, Gowrishankar Chindalore, Cheong Hong
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Patent number: 7262997Abstract: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.Type: GrantFiled: July 25, 2005Date of Patent: August 28, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Jane A. Yater, Gowrishankar L. Chindalore, Cheong M. Hong
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Patent number: 7256454Abstract: An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.Type: GrantFiled: July 25, 2005Date of Patent: August 14, 2007Assignee: Freescale Semiconductor, IncInventors: Jane A. Yater, Gowrishankar L. Chindalore, Cheong M. Hong
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Publication number: 20070018229Abstract: An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.Type: ApplicationFiled: July 25, 2005Publication date: January 25, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Jane Yater, Gowrishankar Chindalore, Cheong Hong
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Publication number: 20070019472Abstract: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.Type: ApplicationFiled: July 25, 2005Publication date: January 25, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Jane Yater, Gowrishankar Chindalore, Cheong Hong
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Patent number: 7064030Abstract: Forming a non-volatile memory device includes providing a semiconductor substrate, forming a masking layer having a first plurality of openings overlying the semiconductor substrate, forming diffusion regions in the semiconductor substrate at locations determined by the masking layer, forming a dielectric within the first plurality of openings, removing the masking layer to form a second plurality of openings, forming sacrificial spacers along edges of the second plurality of openings and adjacent to the dielectric, forming a separating dielectric to separate the sacrificial spacers within each of the second plurality of openings, forming a sacrificial protection layer overlying the separating dielectric, removing the sacrificial spacers, removing the sacrificial protection layer, forming at least two memory storage regions within each of the second plurality of openings, and forming a common control electrode overlying the at least two memory storage regions.Type: GrantFiled: October 8, 2004Date of Patent: June 20, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Gowrishankar L. Chindalore, Jane A. Yater
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Publication number: 20060079051Abstract: Forming a non-volatile memory device includes providing a semiconductor substrate, forming a masking layer having a first plurality of openings overlying the semiconductor substrate, forming diffusion regions in the semiconductor substrate at locations determined by the masking layer, forming a dielectric within the first plurality of openings, removing the masking layer to form a second plurality of openings, forming sacrificial spacers along edges of the second plurality of openings and adjacent to the dielectric, forming a separating dielectric to separate the sacrificial spacers within each of the second plurality of openings, forming a sacrificial protection layer overlying the separating dielectric, removing the sacrificial spacers, removing the sacrificial protection layer, forming at least two memory storage regions within each of the second plurality of openings, and forming a common control electrode overlying the at least two memory storage regions.Type: ApplicationFiled: October 8, 2004Publication date: April 13, 2006Inventors: Gowrishankar Chindalore, Jane Yater
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Patent number: 6969883Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).Type: GrantFiled: September 27, 2004Date of Patent: November 29, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Gowrishankar L. Chindalore, Rajesh A. Rao, Jane A. Yater
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Patent number: 6964902Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.Type: GrantFiled: February 26, 2004Date of Patent: November 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Robert F. Steimle, Jane A. Yater, Gowrishankar L. Chindalore, Craig T. Swift, Steven G. H. Anderson, Ramachandran Muralidhar
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Patent number: 6955967Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).Type: GrantFiled: June 27, 2003Date of Patent: October 18, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Gowrishankar L. Chindalore, Rajesh A. Rao, Jane A. Yater
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Publication number: 20050191808Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.Type: ApplicationFiled: February 26, 2004Publication date: September 1, 2005Inventors: Robert Steimle, Jane Yater, Gowrishankar Chindalore, Craig Swift, Steven Anderson, Ramachandran Muralidhar
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Publication number: 20050041503Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).Type: ApplicationFiled: September 27, 2004Publication date: February 24, 2005Inventors: Gowrishankar Chindalore, Rajesh Rao, Jane Yater
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Publication number: 20050007820Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).Type: ApplicationFiled: June 27, 2003Publication date: January 13, 2005Inventors: Gowrishankar Chindalore, Rajesh Rao, Jane Yater