Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies, each die comprising one integrated circuit. The process comprises: disposing a coating upon the wafer; removing at least a portion of the coating to expose regions of the wafer, along which the wafer is to be diced, to form a workpiece; disposing the workpiece upon a platen within a processing chamber; plasma treating the workpiece with a set of plasma treatment conditions to etch a portion of the exposed regions of the wafer to form a wafer groove which extends laterally beneath the coating to form an undercut; and plasma etching the workpiece with a set of plasma etch conditions, which are different to the plasma treatment conditions, to etch through the wafer and dice the wafer along the wafer groove.

Abstract: An additive-containing aluminium nitride film is plasma etched. The additive-containing aluminium nitride film contains an additive element selected from scandium, yttrium or erbium. A workpiece is placed upon a platen within a plasma chamber. The workpiece includes a substrate having an additive-containing aluminium nitride film deposited thereon and a mask disposed upon the additive-containing aluminium nitride film, which defines at least one trench. A first etching gas is introduced into the chamber with a first flow rate, a second etching gas is introduced into the chamber with a second flow rate, and a plasma is established within the chamber to etch the additive-containing aluminium nitride film exposed within the trench. The first etching gas comprises boron trichloride and the second etching gas comprises chlorine. A ratio of the first flow rate to the second flow rate is greater than or equal to 1:1.

Abstract: A metallic feature on a substrate is subjected to a plasma dicing process and is cleaned. The workpiece has a carrier sheet attached to a frame member. The carrier sheet carries the substrate. The workpiece is provided on a workpiece support disposed within a chamber of an inductively coupled plasma apparatus. A sputter etch step is performed, including introducing a sputter gas or gas mixture into the chamber and sustaining an inductively coupled plasma of the sputter gas or gas mixture so as to sputter etch the substrate. A chemical etch step also is performed, including introducing O2 gas and/or O3 gas) into the chamber and sustaining an inductively coupled plasma of the O2 and/or O3 gas) so as to chemically etch the substrate. The sputter etch step and chemical etch step can be repeated.

Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies, each die comprising one integrated circuit. The process comprises: disposing a coating upon the wafer; removing at least a portion of the coating to expose regions of the wafer, along which the wafer is to be diced, to form a workpiece; disposing the workpiece upon a platen within a processing chamber; plasma treating the workpiece with a set of plasma treatment conditions to etch a portion of the exposed regions of the wafer to form a wafer groove which extends laterally beneath the coating to form an undercut; and plasma etching the workpiece with a set of plasma etch conditions, which are different to the plasma treatment conditions, to etch through the wafer and dice the wafer along the wafer groove.

Abstract: A method is for plasma etching one or more dicing lanes in a silicon substrate having a backside metal layer attached thereto. The method includes performing a main etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated to produce dicing lanes having scalloped sidewalls, and switching to performing a secondary etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated until the backside metal layer is reached. The amount of silicon removed in one etch step during the secondary etch is half or less than half of the amount of silicon removed in one etch step during the main etch.

Abstract: A method is for etching a semiconductor substrate to reveal one or more features buried in the substrate. The method includes performing a first etch step using a plasma in which a bias power is applied to the substrate to produce an electrical bias, performing a second etch step without a bias power or with a bias power which is lower than the bias power applied during the first etch step, and alternately repeating the first and second etch steps.

Abstract: Novel hour and minute hands for teaching reading and passage of time on an analog timepiece. The invention comprises hour and minute hands located centrally and pivotally on the timepiece. The hour hand having at its outer tip a shape through which the hour numerals can be read. The shaft of the hour hand being of a length such that the shape at the tip highlights the correct hour numeral. The shape is sized and positioned on the tip of the hour hand such that when the shaft is set to normal hour hand positions, the correct hour numeral is visible through the shape. The minute hand having at its outer tip a shape through which the minute numerals can be read. The minute hand being of a length such that the hollow shape highlights the correct minute numeral.

Abstract: A solenoidal magnetic field generated by a coil around the upper chamber A acts as a magnetic plasma attenuator. By judicious adjustment of the magnetic field strength, a dense plasma region forms inside the tube and adjacent to an antenna and is at least partially trapped by the field lines. These field lines intersect the wall of the upper chamber near or on the lid, and either on the upper chamber wall near its base, or on the lid or upper walls of the lower chamber. Significant numbers of radicals can be created in the upper chamber, which then diffuse into the lower chamber. The associated ion flux is reduced, however, because of losses where the field lines intersect the walls, thereby ensuring that the ratio of ion numbers to radical numbers reaching the wafer is reduced.

Abstract: A sidewall passivation layer is deposited on an etched feature in a semiconductor substrate with a hydrocarbon deposition gas by introducing H2, determining certain mixture percentages for the hydrocarbon gas/H2 mix at which the etch rate for the substrate peaks, the etch rate begins to rise from a generally steady state, and/or the etch rate falls to zero, and then maintaining the mixture percentage within a selected range. Where the hydrocarbon gas/H2 mix is maintained at a percentage between the steady-state etch rate percentage and the peak etch rate percentage, then relatively high ion energies are used. Where the hydrocarbon gas/H2 mix is maintained at a percentage between the peak etch rate percentage and the percentage where the etch rate falls to zero, then relatively low ion energies are used.

Abstract: There is disclosed a method and apparatus for etching a substrate. The method comprises the steps of etching a substrate or alternately etching and depositing a passivation layer. A bias frequency, which may be pulsed, may be applied to the substrate and may be at or below the ion plasma frequency.

Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.