Patents by Inventor Janet Kirkland

Janet Kirkland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lid attach process
    Patent number: 8865527
    Abstract: Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: October 21, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Maxat Touzelbaev, Janet Kirkland
  • LID ATTACH PROCESS
    Publication number: 20130309814
    Abstract: Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.
    Type: Application
    Filed: July 26, 2013
    Publication date: November 21, 2013
    Inventors: Seah Sun Too, Maxat Touzelbaev, Janet Kirkland
  • Lid attach process
    Patent number: 8497162
    Abstract: Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: July 30, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Maxat Touzelbaev, Janet Kirkland
  • Void reduction in indium thermal interface material
    Patent number: 7999394
    Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
  • Void Reduction in Indium Thermal Interface Material
    Publication number: 20100117222
    Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
    Type: Application
    Filed: December 15, 2009
    Publication date: May 13, 2010
    Inventors: Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
  • Void reduction in indium thermal interface material
    Patent number: 7651938
    Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: January 26, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
  • Void Reduction in Indium Thermal Interface Material
    Publication number: 20070284737
    Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 13, 2007
    Inventors: Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
  • Ball grid array with inexpensive threaded secure locking mechanism to allow removal of a threaded heat sink therefrom
    Patent number: 5885848
    Abstract: An integrated circuit package having a die supported on a ball grid array substrate and wire bonds electrically connecting the die to the substrate. Supported on the substrate is a lock ring having a threaded opening encircling the die. Encapsulant covers the die and the wire bonds and adheres the lock ring to the substrate. A heat sink having a threaded portion can be threaded into the lock ring into an operative cooling position relative to the die and subsequently to an unthreaded removed position. When in the latter position, a repair station can be positioned over the package and the solder balls are accessible for hot gas melting thereof for removal (or replacement) of the package from the underlying motherboard.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: March 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Janet Kirkland, Mark R. Schneider
  • Ball grid array package with inexpensive threaded secure locking mechanism to allow removal of a threaded heat sink therefrom
    Patent number: 5789813
    Abstract: An integrated circuit package having a die supported on a ball grid array substrate and wire bonds electrically connecting the die to the substrate. Supported on the substrate is a lock ring having a threaded opening encircling the die. Encapsulant covers the die and the wire bonds and adheres the lock ring to the substrate. A heat sink having a threaded portion can be threaded into the lock ring into an operative cooling position relative to the die and subsequently to an unthreaded removed position. When in the latter position, a repair station can be positioned over the package and the solder balls are accessible for hot gas melting thereof for removal (or replacement) of the package from the underlying motherboard.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: August 4, 1998
    Assignee: LSI Logic Corporation
    Inventors: Janet Kirkland, Mark R. Schneider