Abstract: A method and apparatus for deriving total lateral diffusion in MOS transistors includes deriving (40) a DC model. The DC model is then verified (42) with a multifinger transistor. The gate of the multifinger transistor is then isolated (44). Voltage pulses are then applied (46) to the multifinger transistor, and the current attributable to the voltage pulses is measured (48). Using the model, estimates of the total lateral diffusion are adjusted (50) until the modelled current matches the measured current. Finally, the complete and accurate AC/DC model can be used (52) by circuit designers to design various circuits that will operate as designed when implemented.

Abstract: The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).

Abstract: The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).

Abstract: Circuitry for controlling the operation of a transient voltage compensation circuit is disclosed. An input buffer circuit 10 is provided which includes a phase splitter transistor 30 having a base at which input signals are applied and an emitter which is coupled to internal ground through Schottky diode 32. A compensation circuit 12 prevents the undesirable switching of transistor 30 during fluctuations in the internal ground voltage level by drawing current from the base of transistor 30 through transistor 42 which has a base connected to a source of current and an emitter connected to internal ground. Transients in the internal ground level effect the turn on of transistor 42 which prevents the turn on of transistor 30 under low input voltage conditions. A compensation control circuit 11 is provided to disable compensation circuit 12 under high input voltage conditions yet allow its normal operation when a low voltage level is applied at the input.