Abstract: A phase digitizing system includes an analog-to-digital converter (ADC), multiple phase accumulators and a processing device. The ADC generates sample segments of digital signal waveform samples based on an analog composite input signal received in a measurement channel, the composite input signal includes a first signal having a first frequency F1 and a second signal imported from a reference channel having a second frequency F2. The processing device is coupled to the phase accumulators, and digitally processes each sample segment with outputs of the phase accumulators, and continually generates digital phase data The processing device further provides increment values to each of the phase accumulators based on the digital phase data, causing an output of a first phase accumulator to represent an instantaneous phase of the first signal, and an output of a second phase accumulator to represent an instantaneous phase of the second signal.

Abstract: A phase digitizing system includes an analog-to-digital converter (ADC), multiple phase accumulators and a processing device. The ADC generates sample segments of digital signal waveform samples based on an analog composite input signal received in a measurement channel, the composite input signal includes a first signal having a first frequency F1 and a second signal imported from a reference channel having a second frequency F2. The processing device is coupled to the phase accumulators, and digitally processes each sample segment with outputs of the phase accumulators, and continually generates digital phase data The processing device further provides increment values to each of the phase accumulators based on the digital phase data, causing an output of a first phase accumulator to represent an instantaneous phase of the first signal, and an output of a second phase accumulator to represent an instantaneous phase of the second signal.

Abstract: A communications module that includes a host interface port, a network medium interface port, and a protocol handler is described. The host interface port is connectable to a media access control interface of a host system. The network medium interface port is connectable to a network medium. The protocol handler is operable to identify a communications protocol compatible with the host system and to adaptively self-configure communications between the host interface port and the network medium interface port in accordance with the identified compatible communications protocol. A method of self-configuring a communications module also is described.

Abstract: Configurable communications modules and methods of making the same are described. In one aspect, a communications module includes a data channel and a termination impedance controller. The data channel is operable to translate data signals in at least one direction between a transmission cable interface and a host device interface. The data channel has a variably configurable termination impedance at a host device node that is connectable to a host device. The termination impedance controller is operable to set the variably configurable termination impedance of the data channel to match the termination impedance to the host system.

Abstract: Handshaking is performed between a first host system and a second host system. First handshaking is performed between a host module within the first host system and a first transceiver within the first host system. The first handshaking includes passing from the first transceiver to the host module dummy information about the second host system. Second handshaking is performed between a second transceiver within the second host system and the first transceiver. The second handshaking includes obtaining, by the first transceiver from the second transceiver, first information about the second host system. Handshaking between the host module and the first transceiver is restarted. This includes passing from the first transceiver to the host module the first information about the second host system. The first information replaces the dummy information passed from the first transceiver to the host module during the first handshaking.

Abstract: A method for compensating jitter in received differential data signals includes recovering a first clock signal from the received differential data signals. Re-timed differential data signals are generated based on the received differential data signals and the first clock signal. A level of jitter in the re-timed differential data signals is detected. A second clock signal is recovered from the re-timed differential data signals. Jitter-compensated differential data signals are generated based on the re-timed differential data signals, the second clock signal, and the detected level of jitter.

Abstract: A circuit is connected between a module and a pair of wires. The circuit includes a first connection line, a second connection line, radio frequency termination circuitry, a first transformer, a second transformer, a tapped inductance and a feedback cancellation filter. The first connection line is for connection to a first wire in the pair of wires. The second connection line is for connection to a second wire in the pair of wires. The radio frequency termination circuitry is connected between the first connection line and the second connection line. The first transformer has a first inductance and a second inductance. A first end of the first inductance is coupled to the first connection line. A first end of the second inductance is coupled to the second connection line. The second transformer includes a first inductance and a second inductance.

Abstract: A method for compensating jitter in received differential data signals includes recovering a first clock signal from the received differential data signals. Re-timed differential data signals are generated based on the received differential data signals and the first clock signal. A level of jitter in the re-timed differential data signals is detected. A second clock signal is recovered from the re-timed differential data signals. Jitter-compensated differential data signals are generated based on the re-timed differential data signals, the second clock signal, and the detected level of jitter.

Abstract: A circuit is connected between a module and a pair of wires. The circuit includes a first connection line, a second connection line, radio frequency termination circuitry, a first transformer, a second transformer, a tapped inductance and a feedback cancellation filter. The first connection line is for connection to a first wire in the pair of wires. The second connection line is for connection to a second wire in the pair of wires. The radio frequency termination circuitry is connected between the first connection line and the second connection line. The first transformer has a first inductance and a second inductance. A first end of the first inductance is coupled to the first connection line. A first end of the second inductance is coupled to the second connection line. The second transformer includes a first inductance and a second inductance.

Abstract: A transceiver module is adapted to be plugged into a port cage within a host system. The transceiver module includes transceiver electronics and a connector attached to the transceiver electronics. The transceiver electronics are sized to fit within the port cage. The connector includes a module portion and a connector jack attached to the module portion. The module portion is sized to fit along with the transceiver electronics within the port cage. The connector jack is sized with dimensions too big to fit within the port cage. The connector jack remains out of the port cage when the transceiver module is placed within the port cage. The connector jack occupies an area larger than an opening of the port cage.

Abstract: A transceiver module is adapted to be plugged into a port cage within a host system. The transceiver module includes transceiver electronics and a connector attached to the transceiver electronics. The transceiver electronics are sized to fit within the port cage. The connector includes a module portion and a connector jack attached to the module portion. The module portion is sized to fit along with the transceiver electronics within the port cage. The connector jack is sized with dimensions too big to fit within the port cage. The connector jack remains out of the port cage when the transceiver module is placed within the port cage. The connector jack occupies an area larger than an opening of the port cage.

Abstract: Handshaking is performed between a first host system and a second host system. First handshaking is performed between a host module within the first host system and a first transceiver within the first host system. The first handshaking includes passing from the first transceiver to the host module dummy information about the second host system. Second handshaking is performed between a second transceiver within the second host system and the first transceiver. The second handshaking includes obtaining, by the first transceiver from the second transceiver, first information about the second host system. Handshaking between the host module and the first transceiver is restarted. This includes passing from the first transceiver to the host module the first information about the second host system. The first information replaces the dummy information passed from the first transceiver to the host module during the first handshaking.

Abstract: A transceiver module is adapted to be plugged into a port cage within a host system. The transceiver module includes transceiver electronics and a connector attached to the transceiver electronics. The transceiver electronics are sized to fit within the port cage. The connector includes a module portion and a connector jack attached to the module portion. The module portion is sized to fit along with the transceiver electronics within the port cage. The connector jack is sized with dimensions too big to fit within the port cage. The connector jack remains out of the port cage when the transceiver module is placed within the port cage. The connector jack occupies an area larger than an opening of the port cage.