Patents by Inventor Jang-Bin Yim

Jang-Bin Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140118246
    Abstract: An electronic device including a photo sensor and a gesture recognition module, and method for the electronic device are provided. The photo sensor emits infrared light, receives reflected light from an external object to which the IR light has been emitted, and generates reflected light data. Then, the gesture recognition module determines a motion or a cover state of an external object as a predefined gesture input type using the reflected light data. The gesture input type includes at least two or more types of motions or cover inputs indicating different cover states of different durations.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 1, 2014
    Applicant: PANTECH CO., LTD.
    Inventors: Seung-Hwan PARK, Woo-Jin Lee, Jang-Bin Yim
  • Publication number: 20140118259
    Abstract: A method for providing a user interface based on a light sensor includes recognizing a motion of an object with respect to a portable device based on a light signal received by at least one light sensor of the portable device and, according to the motion of the object, controlling an application of the portable device. A portable device to provide a user interface based on a light sensor includes at least one light sensor to recognize a motion of an object with respect to the portable device based on a light signal received by at least one light sensor and a control unit to control an application of the portable device according to the motion of the object.
    Type: Application
    Filed: October 31, 2013
    Publication date: May 1, 2014
    Applicant: Pantech Co., Ltd.
    Inventors: Dong Hwa PAEK, Myo Hyeon GYEONG, Jang Bin YIM
  • Publication number: 20090184391
    Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 23, 2009
    Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
  • Patent number: 7510914
    Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 31, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
  • Publication number: 20080214009
    Abstract: Methods of forming a recess structure having a gentle curvature are provided. Such methods include forming a hard mask on a substrate, forming a first preliminary recess on the substrate using the hard mask as an etching mask and forming a spacer on a sidewall of the first preliminary recess. Methods may include forming a second preliminary recess from the first preliminary recess using the spacer as an etching mask and forming the recess structure having an enlarged lower portion from the second preliminary recess using the spacer as an etching mask.
    Type: Application
    Filed: January 28, 2008
    Publication date: September 4, 2008
    Inventors: Chi-Hoon Lee, Jong-Chul Park, Tae-Woo Lee, Tae-Woo Kang, Jang-Bin Yim
  • Publication number: 20070184694
    Abstract: Example embodiments relate to a wiring structure, a semiconductor device and methods of forming the wiring structure. The wiring structure may include a first contact plug, a second contact plug, a protecting layer pattern and an insulating structure. The first contact plug may be provided on a semiconductor substrate. The second contact plug may be provided on the first contact plug to be electrically connected to the first contact plug. The protecting layer pattern may encompass an upper sidewall of the first contact plug and a sidewall of the second contact plug to retard chemicals from infiltrating into an interface between the first and second contact plugs. The insulating structure may encompass the first contact plug, the second contact plug and the protecting layer pattern.
    Type: Application
    Filed: November 3, 2006
    Publication date: August 9, 2007
    Inventors: Jong-Kyu Kim, Jong-Chul Park, Jang-Bin Yim, Sang-Dong Kwon, Ki-Jeong Kim, Sung-Gil Choi
  • Publication number: 20070066056
    Abstract: Example embodiments of the present invention provide a method of removing a photoresist and a method of manufacturing a semiconductor device using the same. In a method of removing a photoresist and a method of manufacturing a semiconductor device, a plasma including active ions and radicals may be generated. The active ions may be modified into directional active ions. The photoresist may be etched using the directional active ions as main etching factors and/or the radicals as subsidiary etching factors. The photoresist may be completely removed from the semiconductor device such as a lower electrode. Thus, the likelihood of an increase in electrical resistance due to residual photoresist may decrease.
    Type: Application
    Filed: June 6, 2006
    Publication date: March 22, 2007
    Inventors: Jong-Kyu Kim, Sung-Gil Choi, Jang-Bin Yim, Sang-Dong Kwon, Ki-Jeong Kim
  • Publication number: 20070047304
    Abstract: In a non-volatile memory device having a relatively high operation performance and a method of manufacturing the same, a substrate may be prepared to include an active region on which a conductive structure is located and defined by a field region in which an isolation layer is formed. A tunnel oxide layer may be formed on the active region of the substrate. A floating gate pattern may be formed on the tunnel oxide layer, and may include a lower part having a first width that is formed on the tunnel oxide layer and an upper part having a second width that is formed on the lower part, where the second width is substantially smaller than the first width. A dielectric layer pattern may be formed on the floating gate pattern, and a control gate pattern may be formed on the dielectric layer pattern. Accordingly, the non-volatile memory device may have an improved efficiency in programming and erasing data.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 1, 2007
    Inventors: Seong-Soo Lee, Young-Wook Park, Jang-Bin Yim, Bum-Su Kim, Du-Hyun Cho
  • Publication number: 20060289899
    Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 28, 2006
    Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi