Abstract: A silicon oxide composite for a secondary battery negative electrode material and a method for manufacturing the same, more particularly, a silicon oxide composite for a secondary battery negative electrode material and a method for manufacturing the same are disclosed. The silicon oxide composite includes MgSiO3 (enstatite) crystals and silicon particles, of which crystal size is from 1 to 25 nm, in a silicon oxide (SiOx, 0<x<2), and a carbon film placed on a surface.

Abstract: The present invention relates to a core-shell structured composite powder for a solid oxide fuel cell (SOFC) and more particularly, to a core-shell structured composite powder for a SOFC having a new structure in which nickel, zirconium and yttrium are stably formed in a core shell structure to improve sinterability and conductivity while preventing a fuel electrode from being deformed due to coarsening and contraction of nickel during operation.

Abstract: A silicon oxide composite for a secondary battery negative electrode material and a method for manufacturing the same, more particularly, a silicon oxide composite for a secondary battery negative electrode material and a method for manufacturing the same are disclosed. The silicon oxide composite includes MgSiO3 (enstatite) crystals and silicon particles, of which crystal size is from 1 to 25 nm, in a silicon oxide (SiOx, 0<x<2), and a carbon film placed on a surface.

Abstract: An EEPROM cell of reduced leakage current during erasure and improved cell topology includes a first conductivity type substrate having a channel region, a trench formed in the channel region of the substrate, first spacers formed on opposed sidewalls of the trench, and a gate oxide film formed at the bottom of the trench between the first spacers. Second conductivity type source/drain regions are formed in the substrate at opposite side of the trench. A tunneling oxide film is further provided on the substrate overlying the drain region and proximate the trench. An insulation film is provided over the entire substrate surface except the trench and the tunneling oxide film. In addition, a floating gate is formed on the insulation film over the source and drain regions, as well as the gate oxide film at the trench bottom. Second spacers are provided on the insulation film at opposed side surfaces of the floating gate.

Abstract: An EEPROM cell of reduced leakage current during erasure and improved cell topology includes a first conductivity type substrate having a channel region, a trench formed in the channel region of the substrate, first spacers formed on opposed sidewalls of the trench, and a gate oxide film formed at the bottom of the trench between the first spacers. Second conductivity type source/drain regions are formed in the substrate at opposite side of the trench. A tunneling oxide film is further provided on the substrate overlying the drain region and proximate the trench. An insulation film is provided over the entire substrate surface except the trench and the tunneling oxide film. In addition, a floating gate is formed on the insulation film over the source and drain regions, as well as the gate oxide film at the trench bottom. Second spacers are provided on the insulation film at opposed side surfaces of the floating gate.

Abstract: A method of manufacturing a nonvolatile memory device having a self-aligned structure includes the steps of forming a gate insulating film on a semiconductor substrate of a first conductivity type. A semiconductor layer is formed on the gate insulating film and etched to form floating gates and a semiconductor pattern between the floating gates. Impurity ions of a second conductivity type are implanted into the same side of the substrate as the floating gate is formed, to form a drain region. A planarizing film is deposited on the substrate and etched until the upper surfaces of the floating gates and the semiconductor pattern are exposed. The semiconductor pattern is removed and impurity ions of the second conductivity type are implanted into the substrate, to form a source region. The planarizing film is removed to expose the floating gate, and a dielectric film is formed thereon. Finally, a control gate is formed on the substrate.