Abstract: A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.

Abstract: A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.

Abstract: An oscillator includes a reference voltage generator configured to generate a reference voltage varying according a change in temperature and an external voltage, a first comparison voltage generator configured to output a first comparison voltage to a first node in response to the reference voltage, a second comparison voltage generator configured to output a second comparison voltage to a second node in response to the reference voltage, a first comparison circuit configured to compare the reference voltage and the first comparison voltage and to generate a first input voltage as a result of the comparison, a second comparison circuit configured to compare the reference voltage and the second comparison voltage and to generate a second input voltage as a result of the comparison, and a clock generator configured to output a clock signal that oscillates in response to the first and second input voltages.

Abstract: A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.

Abstract: A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.

Abstract: An oscillator includes a reference voltage generator configured to generate a reference voltage varying according a change in temperature and an external voltage, a first comparison voltage generator configured to output a first comparison voltage to a first node in response to the reference voltage, a second comparison voltage generator configured to output a second comparison voltage to a second node in response to the reference voltage, a first comparison circuit configured to compare the reference voltage and the first comparison voltage and to generate a first input voltage as a result of the comparison, a second comparison circuit configured to compare the reference voltage and the second comparison voltage and to generate a second input voltage as a result of the comparison, and a clock generator configured to output a clock signal that oscillates in response to the first and second input voltages.