Patents by Inventor Jang-Hyun You
Jang-Hyun You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10854623Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: GrantFiled: July 12, 2019Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
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Publication number: 20190341396Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: ApplicationFiled: July 12, 2019Publication date: November 7, 2019Inventors: Jang Hyun YOU, Jin Taek PARK, Taek Soo SHIN, Sung Yun LEE
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Patent number: 10355010Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: GrantFiled: October 17, 2016Date of Patent: July 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
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Publication number: 20170207232Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: ApplicationFiled: October 17, 2016Publication date: July 20, 2017Inventors: Jang Hyun YOU, Jin Taek PARK, Taek Soo SHIN, Sung Yun LEE
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Patent number: 9553098Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.Type: GrantFiled: September 18, 2015Date of Patent: January 24, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Hyun You, Hyeong Park, Bongtae Park, Jeehoon Han
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Patent number: 9362306Abstract: According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.Type: GrantFiled: December 28, 2015Date of Patent: June 7, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jintaek Park, Sunghoi Hur, Jang-Hyun You
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Patent number: 9330913Abstract: A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.Type: GrantFiled: October 27, 2010Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Hyun You, Jong-Min Lee, Dong-Hwa Kwak, Tae-Yong Kim, Jong-Hoon Na, Young-Woo Park, Dong-Sik Lee, Jee-Hoon Han
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Publication number: 20160111441Abstract: According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.Type: ApplicationFiled: December 28, 2015Publication date: April 21, 2016Inventors: Jintaek Park, Sunghoi Hur, Jang-Hyun You
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Patent number: 9299718Abstract: According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.Type: GrantFiled: February 12, 2015Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jintaek Park, Sunghoi Hur, Jang-Hyun You
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Publication number: 20160013196Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.Type: ApplicationFiled: September 18, 2015Publication date: January 14, 2016Inventors: Jang-Hyun YOU, Hyeong PARK, Bongtae PARK, Jeehoon HAN
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Publication number: 20150340376Abstract: According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.Type: ApplicationFiled: February 12, 2015Publication date: November 26, 2015Inventors: Jintaek PARK, Sunghoi HUR, Jang-Hyun YOU
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Patent number: 9171853Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.Type: GrantFiled: March 7, 2014Date of Patent: October 27, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Hyun You, Hyeong Park, Bongtae Park, Jeehoon Han
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Publication number: 20150236111Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.Type: ApplicationFiled: April 10, 2015Publication date: August 20, 2015Inventors: Chang-Hyun Lee, Byung-Kyu Cho, Jang-Hyun You, Albert Fayrushin
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Patent number: 8951881Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.Type: GrantFiled: May 16, 2014Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Sik Lee, Jang-Hyun You, Jee-Hoon Han, Young-Woo Park, Sung-Hoi Hur, Sang-Ick Joo
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Patent number: 8878332Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.Type: GrantFiled: April 9, 2014Date of Patent: November 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Na, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park
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Publication number: 20140252444Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.Type: ApplicationFiled: March 7, 2014Publication date: September 11, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Hyun YOU, Hyeong PARK, Bongtae PARK, Jeehoon HAN
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Publication number: 20140248755Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.Type: ApplicationFiled: May 16, 2014Publication date: September 4, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Sik Lee, Jang-Hyun You, Jee-Hoon Han, Young-Woo Park, Sung-Hoi Hur, Sang-Ick Joo
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Publication number: 20140231953Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.Type: ApplicationFiled: April 9, 2014Publication date: August 21, 2014Inventors: Jong-Hoon NA, Young-Woo PARK, Dong-Hwa KWAK, Tae-Yong KIM, Jee-Hoon HAN, Jang-Hyun YOU, Dong-Sik LEE, Su-Jin PARK
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Patent number: 8753955Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.Type: GrantFiled: November 21, 2011Date of Patent: June 17, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Sik Lee, Jang-Hyun You, Jee-Hoon Han, Young-Woo Park, Sung-Hoi Hur, Sang-Ick Joo
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Patent number: 8748286Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.Type: GrantFiled: August 4, 2011Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Na, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park