Abstract: The present invention relates to a poly(organophosphazene)-superparamagnetic nanoparticle complex including a biodegradable and thermosensitive poly(organophosphazene) and a iron oxide (Fe3O4, Magnetite)-series ferrite superparamagnetic nanoparticle, a preparation method, and uses of carrying a physiologically-active material, a bio-material and a biomaterial for cancer hyperthermia. The iron oxide is used as a MRI contrast agent for T?2 and T2* weighted image, and the poly(organophosphazene) shows a sol-to-gel behavior depending upon the temperature change. The complex is a bound-type where the superparamagnetic ferrite nanoparticle is bonded to phosphazene-based polymer via hydrophobic binding, and a mixed-type where the superparamagnetic ferrite nanoparticle is physically mixed with the phosphazene-based polymer.

Abstract: A display panel includes a gate line extending substantially in a first direction, a first data line extending in a second direction substantially perpendicular to the first direction and a first switching element comprising a first electrode, a second electrode and a channel layer, where an end portion of the first electrode has a first edge oriented substantially perpendicular to a direction of extension of the first electrode, and the second electrode extends in a direction substantially opposite to the first electrode and an end portion of the second electrode has a second edge oriented substantially perpendicular to a direction of extension of the second electrode, and the channel layer substantially entirely covers both a lower surface of the first electrode and a lower surface of the second electrode.

Abstract: A method of manufacturing a liquid crystal display includes: preparing a lower mother substrate, where lower cells, each including a thin film transistor, are provided on the lower mother substrate, and a lower alignment layer is disposed on the lower cells; preparing an upper mother substrate, where upper cells corresponding to the lower cells are provided on the upper mother substrate, and an upper alignment layer is disposed on the upper cells; providing a mother substrate assembly by providing a liquid crystal mixture layer between the lower and upper mother substrates and combining the lower and upper mother substrates; providing a pretilt of the liquid crystals by applying a voltage to a voltage application unit of the lower mother substrate; and curing an alignment supporting agents in the liquid crystal mixture layer or the lower and upper alignment layers by irradiating light to a side of the mother substrate assembly.

Abstract: A display device includes gate lines, data lines, first wires and second wires extending in the directions of the gate lines and data lines, and pixels having a first subpixel and a second subpixel each. The first subpixel has a first subpixel electrode and a first switching element, and the second subpixel has a second subpixel electrode and second and third switching elements. The control terminals of the three switching elements are connected to the same gate line, and the input terminals of the first and second switching elements are connected to the same data line. The first and second switching elements have output terminals connected to the first and second subpixel electrodes, respectively. The second switching element's output terminal connects to the third switching element, which has an output terminal connected to a second wire. The first wires and the second wires are connected in a pixel.

Abstract: An array substrate includes a base substrate and a contact part. The contact part is disposed on the base substrate. The contact part includes a first metal pattern, a disconnection control pattern and a connecting pattern. The second metal pattern is disposed on a layer different from the first metal pattern, the disconnection control pattern overlaps a side surface of the second metal pattern and a connecting pattern is formed on the first and second metal patterns and the disconnection control pattern and connects the first metal pattern with the second metal pattern.

Abstract: A display device includes a display area and a non-display area, a first alignment layer disposed on a first substrate, a second alignment layer disposed on a second substrate, a liquid crystal layer disposed between the first alignment layer and the second alignment layer; and a groove disposed in the non-display area of the second substrate to correspond to at least a portion of an end portion of the second alignment layer. The groove is provided along at least one side of the display area and is configured to be filled by an alignment solution used to from the second alignment layer and prevent the alignment solution from dispersing to other areas of the second substrate.

Abstract: A display device comprising a display area and non-display area is provided. The display device includes a first substrate, a second substrate, a liquid crystal layer, and a connection part. The first substrate includes a first base substrate, a wiring part formed on the first base substrate, and a pixel electrode connected to a portion of the wiring part, the pixel electrode disposed in the display area. The second substrate includes a second base substrate, and a common electrode formed on the second base substrate. The liquid crystal layer is disposed between the first base substrate and the second base substrate. The connection part is formed between the first base substrate and the second base substrate connecting the common electrode and the portion of the wiring part, wherein the common electrode comprises an electric field control pattern formed in the non-display area between the connection part and the display area.

Abstract: A method of manufacturing a liquid crystal display includes: preparing a lower mother substrate, where lower cells, each including a thin film transistor, are provided on the lower mother substrate, and a lower alignment layer is disposed on the lower cells; preparing an upper mother substrate, where upper cells corresponding to the lower cells are provided on the upper mother substrate, and an upper alignment layer is disposed on the upper cells; providing a mother substrate assembly by providing a liquid crystal mixture layer between the lower and upper mother substrates and combining the lower and upper mother substrates; providing a pretilt of the liquid crystals by applying a voltage to a voltage application unit of the lower mother substrate; and curing an alignment supporting agents in the liquid crystal mixture layer or the lower and upper alignment layers by irradiating light to a side of the mother substrate assembly.

Abstract: A liquid crystal display is provided. A liquid crystal display includes: a first substrate; a thin film transistor disposed on the first substrate; and a first electrode disposed on the thin film transistor and connected to an output terminal of the thin film transistor, wherein the first electrode includes a first region and a second region each including a plurality of minute branches separated from each other by open parts, portions of at least two minute branches among the plurality of minute branches are connected to form a plurality of minute plate branches, and wherein the minute plate branch has a wider width than a minute branch.

Abstract: A transparent display apparatus includes a display panel including a plurality of pixels arranged in rows and columns, a plurality of gate lines, a plurality of data lines including first and second data lines, a gate driver, and a data driver. Each of the pixels comprises sub-pixels arranged in a row direction, each gate line is operatively coupled to sub-pixels arranged in a corresponding row, and each first and second data line is operatively coupled to sub-pixels arranged in a corresponding column. The gate driver sequentially applies a gate signal to the pixels through the gate lines. The data driver applies sub-data signals to the sub-pixels through the first data lines, and applies down data signals to the sub-pixels through the second data lines. Each of the down data signals has a voltage level lower than a voltage level of a corresponding sub-data signal.

Abstract: A display device includes gate lines, data lines, first wires and second wires extending in the directions of the gate lines and data lines, and pixels having a first subpixel and a second subpixel each. The first subpixel has a first subpixel electrode and a first switching element, and the second subpixel has a second subpixel electrode and second and third switching elements. The control terminals of the three switching elements are connected to the same gate line, and the input terminals of the first and second switching elements are connected to the same data line. The first and second switching elements have output terminals connected to the first and second subpixel electrodes, respectively. The second switching element's output terminal connects to the third switching element, which has an output terminal connected to a second wire. The first wires and the second wires are connected in a pixel.

Abstract: An array substrate includes a base substrate and a contact part. The contact part is disposed on the base substrate. The contact part includes a first metal pattern, a disconnection control pattern and a connecting pattern. The second metal pattern is disposed on a layer different from the first metal pattern, the disconnection control pattern overlaps a side surface of the second metal pattern and a connecting pattern is formed on the first and second metal patterns and the disconnection control pattern and connects the first metal pattern with the second metal pattern.

Abstract: An exemplary embodiment of the present invention relates to a display panel having a plurality of pixels, the display panel including a first substrate, and a color filter including a plurality of first color filters disposed on the first substrate and a second color filter having a black color and disposed in the same layer as the first color filters.

Abstract: The present invention provides a liquid crystal display (LCD). The LCD includes: a liquid crystal panel that includes a plurality of gate lines; and a gate driver that includes a plurality of stages, which are connected to the gate lines, respectively, and sequentially provide a plurality of gate signals to the gate lines, respectively, and a first dummy stage and a second dummy stage that are separated from each other, wherein the first dummy stage is enabled by a carry signal of one of the stages, and the second dummy stage is enabled by a carry signal of the first dummy stage and initializes each of the stages.

Abstract: A liquid crystal display (“LCD”) capable of improving display quality includes a first insulating substrate, gate wiring lines formed on the first insulating substrate and extending in a first direction, pixel electrodes, each of which includes first and second sub-pixel electrodes that are, respectively, applied with different data voltages from first and second wiring lines insulated from and crossing the gate wiring lines, extending in a second direction and an insulting layer interposed between the first data wiring line and the second data wiring line overlapped by the first data wiring line. Therefore, an aperture ratio of the LCD increase because the first data wiring line overlapped the second data wiring line have less area between pixel electrodes. A display quality of the LCD improves.

Abstract: The present invention relates to a poly(organophosphazene)-superparamagnetic nanoparticle complex including a biodegradable and thermosensitive poly(organophosphazene) and a iron oxide (Fe3O4, Magnetite)-series ferrite superparamagnetic nanoparticle, a preparation method, and uses of carrying a physiologically-active material, a bio-material and a biomaterial for cancer hyperthermia. The iron oxide is used as a MRI contrast agent for T-2 and T2* weighted image, and the poly(organophosphazene) shows a sol-to-gel behavior depending upon the temperature change. The complex is a bound-type where the superparamagnetic ferrite nanoparticle is bonded to phosphazene-based polymer via hydrophobic binding, and a mixed-type where the superparamagnetic ferrite nanoparticle is physically mixed with the phosphazene-based polymer.

Abstract: The present invention relates to a thin film transistor array panel that includes an organic layer formed on a data line and a drain electrode disposed on a color filter. A thickness of a portion of the organic layer around a contact hole exposing a portion of the drain electrode is similar to a thickness of a portion of the organic layer around a contact hole exposing a portion of the data line. Having approximately the same thickness can prevent non-uniform etching of the organic layer around contact holes and deterioration of the thin film transistor array panel.

Abstract: A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.

Abstract: A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.

Abstract: An exemplary embodiment of the present invention relates to a display panel having a plurality of pixels, the display panel including a first substrate, and a color filter including a plurality of first color filters disposed on the first substrate and a second color filter having a black color and disposed in the same layer as the first color filters.