Abstract: A method for managing a broadcast receiving apparatus standby mode according to external signaling is provided. The method includes: generating a power management descriptor that a broadcast receiving apparatus refers to in order to perform a standby mode; and transmitting the generated power management descriptor to the broadcast receiving apparatus. Accordingly, since the broadcast receiving apparatus manages the standby mode more effectively, standby power consumed in the standby mode is further reduced and thus power saving effect can be achieved.

Abstract: A method for managing a broadcast receiving apparatus standby mode according to external signaling is provided. The method includes: generating a power management descriptor that a broadcast receiving apparatus refers to in order to perform a standby mode; and transmitting the generated power management descriptor to the broadcast receiving apparatus. Accordingly, since the broadcast receiving apparatus manages the standby mode more effectively, standby power consumed in the standby mode is further reduced and thus power saving effect can be achieved.

Abstract: A dual port memory device having a plurality of memory blocks which are divided from a memory cell array formed on same semiconductor substrate comprises a first memory block which shares a RAM port with a second memory block adjacent to one part thereof and also shares a SAM port with a third memory block adjacent to the other part thereof.

Abstract: A video RAM device which is easily manufactured to be compatible with a video system, irrespective of the type of video RAM controller used in the system. The video RAM is freely changeable in a manufacturing step to operate as either a half SAM device or as a full SAM device to conform to the type of video RAM controller used or current demand of customers of video RAM devices, depending upon an internal addressing condition. The video RAM device includes a serial access memory (SAM) and a random access memory (RAM) each having interleaved groups of memory cells which are interleaved with respect to a serial output sequence from the SAM. A first interleaved group is represented by memory cells having an address with a most significant bit being at one logic level, and a second interleaved group is represented by memory cells having an address with a most significant bit being at an opposite logic level.

Abstract: A semiconductor memory device having a plurality of memory blocks and a plurality of I/O control circuits operatively associated with respective ones of the memory blocks. Each of the I/O control circuits includes a flash write enable signal generator responsive to a flash write mode indication signal and a respective memory block address signal, for generating a memory block specific flash write enable signal. Each of the I/O control circuits further includes a plurality of first column selectors connected between respective first alternate pairs of bit lines and respective first data input/output lines, a plurality of second column selectors connected between respective second alternate pairs of bit lines and respective second data input/output lines, and a plurality of flash write control logic circuits responsive to the memory block specific flash write enable signal and a respective one of a plurality of column select signals for generating a corresponding plurality of column selector drive signals.

Abstract: A data output buffer circuit includes a pair of data lines respectively applied with a noninverted data signal and an inverted data signal and an output gate circuit for gating the noninverted and inverted data signals in response to an output enable signal. A pull-up/pull-down NMOS transistor pair is connected in series between a first supply voltage and a ground voltage. A supply voltage converter circuit generates a constant second supply voltage so long as said first supply voltage is above a predetermined minimum level. A bootstrap circuit is precharged by the second supply voltage for driving the pull-up NMOS transistor with a boosted voltage level when the non-inverted data signal is a logic "HIGH" state.

Abstract: If a defect is occurred in a certain normal memory when a dual-port memory device having a first and a second normal memory carries out the data transfer by a first and a second transfer signal, either of the first or the second transfer signals which corresponds to the defective normal memory is selected by a redundant transfer signal generator. The redundant transfer signal makes a redundant transfer gate turned on to transfer the data between a redundant RAM and a redundant SAM, and to substitute for the defective part of the normal memory. Thus, the defective part of the normal memory means which is occurred during the split transfer of data can be replaced by the single redundant circuit, so that the size of the memory device becomes minimize.