Abstract: A method and the associated devices for implementing a suspend-to-RAM (STR) mode of operation in a computer system utilizing the self-refreshing capability of synchrotron DRAM. To switch into the STR mode of operation, system memory data in a first control chip (the north bridge) is first transferred to a memory unit under the direction of a second control chip (the south bridge). The voltage level at the clock-enable pin of the system memory is pulled down under the direction of the south bridge or the north bridge. Power to the north bridge is cut upon receiving a signal from a basic input/output system.

Abstract: A voltage converter for supporting a suspension-to-RAM (STR) mode of power management. The voltage converter has a flip-flop, a resume & initialization logic circuit for producing a resume signal, a STR logic circuit for producing a STR signal, a first voltage-conversion unit and a second voltage-conversion unit. An output terminal of the resume & initialization logic circuit is connected to a first input terminal of the flip-flop. An output terminal of the STR logic circuit is connected to a second input terminal of the flip-flop. An output terminal of the flip-flop is connected to the first voltage-conversion unit, and a complementary output terminal of the flip-flop is connected to the second voltage-conversion unit. A suspension voltage or a power voltage is applied to the voltage pin of a system memory depending on the mode of power management.