Patents by Inventor Jang-Mee Seo

Jang-Mee Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9542978
    Abstract: A semiconductor package includes: a plurality of memory packages which are arranged on a substrate; and a logic chip, which has a rhombus shape including first through fourth corners and first through fourth sides connecting the first through fourth corners, is arranged adjacent to the plurality of memory packages, and includes a plurality of terminals that are electrically connected to the plurality of memory packages, as seen on a plan view of the semiconductor package, wherein the plurality of terminals include system address terminals which are adjacent to the first corner of the logic chip and first and second system data terminals which are respectively arranged on the first and second sides contacting the first corner. Another semiconductor package and a method of fabrication are disclosed.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-won Lee, Jang-mee Seo, In-won O
  • Publication number: 20160049176
    Abstract: A semiconductor package includes: a plurality of memory packages which are arranged on a substrate; and a logic chip, which has a rhombus shape including first through fourth corners and first through fourth sides connecting the first through fourth corners, is arranged adjacent to the plurality of memory packages, and includes a plurality of terminals that are electrically connected to the plurality of memory packages, as seen on a plan view of the semiconductor package, wherein the plurality of terminals include system address terminals which are adjacent to the first corner of the logic chip and first and second system data terminals which are respectively arranged on the first and second sides contacting the first corner. Another semiconductor package and a method of fabrication are disclosed.
    Type: Application
    Filed: June 2, 2015
    Publication date: February 18, 2016
    Inventors: Jong-won LEE, Jang-mee SEO, In-won O
  • Patent number: 8188582
    Abstract: Provided are a lead frame, semiconductor device, and methods of manufacturing the same. The lead frame may include a die pad having at least three pair of sides parallel with each other, and a plurality of inner leads spaced apart from a circumference of the die pad, arranged in a radial shape with respect to a center of the die pad, and having the ends form inner lead connection surfaces parallel with at least one pair of sides of the die pad. In addition, there may be provided a semiconductor device having the lead frame. Accordingly, a semiconductor chip may be positioned on a die pad. The plurality of inner leads may be electrically connected to the semiconductor chip through wires. The semiconductor device may further include a molding resin for surrounding top and bottom surfaces of the lead frame and filling in an interior thereof.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jang-Mee Seo
  • Publication number: 20080258280
    Abstract: Provided are a lead frame, semiconductor device, and methods of manufacturing the same. The lead frame may include a die pad having at least three pair of sides parallel with each other, and a plurality of inner leads spaced apart from a circumference of the die pad, arranged in a radial shape with respect to a center of the die pad, and having the ends form inner lead connection surfaces parallel with at least one pair of sides of the die pad. In addition, there may be provided a semiconductor device having the lead frame. Accordingly, a semiconductor chip may be positioned on a die pad. The plurality of inner leads may be electrically connected to the semiconductor chip through wires. The semiconductor device may further include a molding resin for surrounding top and bottom surfaces of the lead frame and filling in an interior thereof.
    Type: Application
    Filed: April 17, 2008
    Publication date: October 23, 2008
    Inventor: Jang-Mee Seo