Abstract: Disclosed is a LiDAR window integrated optical filter that includes a window of a polymer material for absorbing a visible light band and transmitting a near-infrared band; and an upper reflective layer and a lower reflective layer formed on the upper surface and the lower surface of the window. The upper reflective layer and the lower reflective layer may be formed in a thin film including titanium dioxide (TiO2) and silicon dioxide (SiO2).

Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Abstract: Described herein is an error correction circuit that includes a syndrome check history manager configured to maintain a history of syndrome checks corresponding to one or more iterations of the iterative decoding scheme. The error correction circuit also includes a trapping set detector configured to compare a trapping set determination policy with the history of syndrome checks to determine whether the history of syndrome checks meets criteria of the trapping set determination policy, while error correction decoding is performed, and determine that a trapping set exists when the history of syndrome checks satisfies the trapping set determination policy. The trapping set determination policy is related to at least one of a change in a syndrome vector, a number of UCNs, and a change in the number of UCNs.

Abstract: Disclosed are devices, systems and methods for error correction encoding and decoding. A memory controller includes an error correction encoder for generating a codeword by performing error correction encoding, using a parity check matrix including a plurality of sub-matrices; and an error correction decoder for performing error correction decoding on a read vector corresponding to the codeword on a column layer basis while sequentially selecting column layers of the parity check matrix used for the error correction encoding, in the error correction decoding, the column layer including a set of columns of the parity check matrix. Rows included in the parity check matrix are grouped into a plurality of row groups, and at most one cyclic permutation matrix (CPM) is included for each column layer in each of the row groups.

Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Abstract: Provided herein may be a circuit for transforming a parity-check matrix of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code, an error correction circuit having the same, and a method of operating the same. The circuit for transforming a parity check matrix of a QC-LDPC code including circulant matrices may include a determination component configured to determine whether a parity-check matrix that is externally input has full rank, a selection component configured to detect linearly dependent rows or columns, among rows or columns of the parity-check matrix based on a result of the determination of the determination component, and select any one row or column from among the linearly dependent rows or columns, and an entry replacement component configured to replace any one of circulant matrices included in the selected one row or column with a zero matrix.

Abstract: The decoder controller includes flip number management section configured to, after a decoding operation for a codeword of a first direction succeeds, decrease flip numbers of all codewords of a second direction which intersect with the codeword of the first direction and have error-probable areas.

Abstract: Provided herein may be an error correction circuit for detecting a trapping set and a method of operating the error correction circuit. The error correction circuit may include a syndrome check history manager configured to maintain a history of syndrome checks corresponding to one or more iterations of the iterative decoding scheme, and a trapping set detector configured to compare a trapping set determination policy with the history of syndrome checks to determine whether the history of syndrome checks meets criteria of the trapping set determination policy, while error correction decoding is performed, and determine that a trapping set exists when the history of syndrome checks satisfies the trapping set determination policy, wherein the trapping set determination policy is related to at least one of a change in a syndrome vector, a number of UCNs, and a change in the number of UCNs.

Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Abstract: An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.

Abstract: Provided herein may be a circuit for transforming a parity-check matrix of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code, an error correction circuit having the same, and a method of operating the same. The circuit for transforming a parity check matrix of a QC-LDPC code including circulant matrices may include a determination component configured to determine whether a parity-check matrix that is externally input has full rank, a selection component configured to detect linearly dependent rows or columns, among rows or columns of the parity-check matrix based on a result of the determination of the determination component, and select any one row or column from among the linearly dependent rows or columns, and an entry replacement component configured to replace any one of circulant matrices included in the selected one row or column with a zero matrix.

Abstract: An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation on a codeword, which is selected by the control unit, in the data chunk, wherein the control unit calculates a first reference value by applying a correction capability value of the first direction to a flag of the first direction, calculates a second reference value by applying a correction capability value of the second direction to a flag of the second direction, selects a priority direction from the first direction and the second direction based on the first reference value and the second reference value, and preferentially selects codewords of the priority direction for decoding operations.

Abstract: A data storage device includes a nonvolatile memory device configured to store a codeword; and a controller configured to read the codeword from the nonvolatile memory device, and perform a decoding process for the codeword, wherein, when performing the decoding process, the controller calculates a flag of the codeword, calculates an expected number of errors by applying an adjustment coefficient to the flag, compares the expected number of errors to an allowed number of errors, and skips or performs a decoding operation for the codeword depending on a comparison result.

Abstract: An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation on a codeword, which is selected by the control unit, in the data chunk, wherein the control unit calculates a first reference value by applying a correction capability value of the first direction to a flag of the first direction, calculates a second reference value by applying a correction capability value of the second direction to a flag of the second direction, selects a priority direction from the first direction and the second direction based on the first reference value and the second reference value, and preferentially selects codewords of the priority direction for decoding operations.

Abstract: An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation on a codeword, which is selected by the control unit, in the data chunk, wherein the control unit calculates a first reference value by applying a correction capability value of the first direction to a flag of the first direction, calculates a second reference value by applying a correction capability value of the second direction to a flag of the second direction, selects a priority direction from the first direction and the second direction based on the first reference value and the second reference value, and preferentially selects codewords of the priority direction for decoding operations.

Abstract: A decoder controller may be provided. The decoder controller may include flip number management section configured to, after a decoding operation for a codeword of a first direction succeeds, decrease flip numbers of all codewords of a second direction which intersect with the codeword of the first direction and have error-probable areas.

Abstract: An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.

Abstract: A data storage device includes a nonvolatile memory device configured to store a codeword; and a controller configured to read the codeword from the nonvolatile memory device, and perform a decoding process for the codeword, wherein, when performing the decoding process, the controller calculates a flag of the codeword, calculates an expected number of errors by applying an adjustment coefficient to the flag, compares the expected number of errors to an allowed number of errors, and skips or performs a decoding operation for the codeword depending on a comparison result.

Abstract: An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation for a codeword selected by the control unit in the data chunk, wherein the control unit preferentially selects, depending on a result of a first decoding operation for a first codeword of the first direction, a second codeword of the second direction or a third codeword of the first direction.

Abstract: An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.